Information

PIC24FJ128GA010 FAMILY
DS80471B-page 14  2009-2011 Microchip Technology Inc.
47. Module: Core (Instruction Set)
If an instruction producing a read-after-write stall
condition is executed inside a REPEAT loop, the
instruction will be executed fewer times than was
intended. For example, this loop:
repeat #0xf
inc [w1],[++w1]
will execute less than 15 times.
Work around
Avoid using REPEAT to repetitively execute
instructions that create a stall condition. Instead,
use a software loop using conditional branches.
Affected Silicon Revisions
48. Module: Memory (Program Space
Visibility)
When accessing data in the PSV area of data
RAM, it is possible to generate a false address
error trap condition by reading data located
precisely at the lower address boundary (8000h).
If data is read using an instruction with an
auto-decrement, the resulting RAM address will be
below the PSV boundary (i.e., at 7FFEh); this will
result in an address error trap.
This false address error can also occur if a 32-bit
MOV instruction is used to read the data at location
8000h.
Work around
Do not use the first location of a PSV page
(address 8000h).
Affected Silicon Revisions
49. Module: I/O (PORTB)
When RB5 is configured as an open-drain output,
it remains in a high-impedance state. The settings
of LATB5 and TRISB5 have no effect on the pin’s
state.
Work around
If open-drain operation is not required, configure
RB5 as a regular I/O (ODCB<5> = 0).
If open-drain operation is required, there are two
options:
• select a different I/O pin for the open-drain
function; or
• place an external transistor on the pin and
configure the pin as a regular I/O.
Affected Silicon Revisions
50. Module: RTCC (Alarm)
Under certain circumstances, the value of the
Alarm Repeat Counter (ALCFGRPT<7:0>) may be
unexpectedly decremented. This happens only
when a byte write to the upper byte of ALCFGRPT
is performed in the interval between a device
POR/BOR and the first edge from the RTCC clock
source.
Work around
Do not perform byte writes on ALCFGRPT,
particularly the upper byte.
Alternatively, wait until one period of the SOSC
has completed before performing byte writes to
ALCFGRPT.
Affected Silicon Revisions
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXXX
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