Information

 2009-2011 Microchip Technology Inc. DS80471B-page 13
PIC24FJ128GA010 FAMILY
42. Module: CRC
If a CRC FIFO overflow occurs, the VWORD
indicator will reset to ‘1’ instead of ‘0’. Further
writes to the FIFO will cause the VWORD indicator
to reset to ‘0’ after seven writes are performed.
Work around
Poll the CRCFUL bit (CRCCON<7>) to ensure that
no writes are performed on the FIFO when it is full.
Affected Silicon Revisions
43. Module: UART (IrDA
®
)
When the UART is configured for IrDA interface
operations (UxMODE<9:8> = 11), the 16x baud
clock signal on the BCLKx pin will only be present
when the module is transmitting. The pin will be
Idle at all other times.
Work around
Configure one of the output compare modules to
generate the required baud clock signal when the
UART is receiving data or in an Idle state.
Affected Silicon Revisions
44. Module: I
2
C
Bit and byte-based operations may not have the
intended affect on the I2CxSTAT register. It is
possible for bit and byte operations performed on
the lower byte of I2CxSTAT to clear the BCL bit
(I2CxSTAT<10>). Bit and byte operation performed
on the upper byte of I2CxSTAT, or on the BCL bit
directly, may not be able to clear the BCL bit.
Work around
Modifications to the I2CxSTAT register should be
done using word writes only. This can be done in
‘C’ by always writing to the register itself and not
the individual bits. For example, the code:
I2C1STAT &= 0xFBFF
forces the compiler to use a word-based operation
to clear the BCL bit. In assembly, it is done by not
using BSET or BCLR instructions. or instructions
with the .b modifier.
Affected Silicon Revisions
45. Module: I
2
C
After the ACKSTAT bit is set, while receiving a
NACK from the master or a slave, it may be
cleared by the reception of a Start or Stop bit.
Work around
Store the value of the ACKSTAT bit immediately
after receiving a NACK.
Affected Silicon Revisions
46. Module: RTCC
When performing writes to the ALCFGRPT register,
some bits may become corrupted. The error occurs
because of desynchronization between the CPU
clock domain and the RTCC clock domain.
The error causes data from the instruction following
the ALCFGRPT instruction to overwrite the data in
ALCFGRPT.
Work around
Always follow writes to the ALCFGRPT register
with an additional write of the same data to a
dummy location. These writes can be performed to
RAM locations, W registers or unimplemented
SFR space.
The optimal way to perform the work around:
1. Read ALCFGRPT into a RAM location.
2. Modify the ALCFGRPT data, as required, in
RAM.
3. Move the RAM value into ALCFGRPT and a
dummy location in back-to-back instructions.
Affected Silicon Revisions
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XX
A2 A3 A4 C1 C2
X
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX