Information

PIC24FJ128GA010 FAMILY
DS80471B-page 12  2009-2011 Microchip Technology Inc.
36. Module: I
2
C (Slave Mode)
During I
2
C Slave mode transactions, the
Data/Address
bit, D/A, may not update during
the data frame. This affects both 7 and 10-Bit
Addressing modes.
I
2
C slave receptions are not affected by this issue.
Work around
Use the Read/Write bit, R/W, and the Transmit
Buffer Full Status Bit, TBF, to determine whether
address or data information is being received.
For more information, see Figure 24-30 and
Figure 24-31 in Section 24. “Inter-Integrated
Circuit™ (I
2
C™)” (DS39702).
Affected Silicon Revisions
37. Module: UART (Auto-Baud)
When an auto-baud is detected, the receive
interrupt may occur twice. The first interrupt occurs
at the beginning of the Start bit and the second
after reception of the Sync field character.
Work around
If a receive interrupt occurs, check the URXDA bit
(UxSTA<0>) to ensure that valid data is available.
On the first interrupt, no data will be present. The
second interrupt will have the Sync field character
(55h) in the receive FIFO.
Affected Silicon Revisions
38. Module: UART (Auto-Baud)
The auto-baud may miscalculate for certain baud
rates and clock speed combinations, resulting in a
BRG value that is 1 greater or less than the
expected value. When UxBRG is less than 50, this
can result in transmission and reception failures
due to introducing error greater than 1%.
Work around
Test auto-baud calculations at various clock speed
and baud rate combinations that would be used in
applications. If an inaccurate UxBRG value is
generated, manually correct the baud rate in user
code.
Affected Silicon Revisions
39. Module: UART
When the UART uses two Stop bits (STSEL = 1),
it may sample the first Stop bit instead of the
second one. If the device being communicated
with is using one Stop bit in its communications,
this may lead to framing errors.
Work around
None.
Affected Silicon Revisions
40. Module: SPI
In SPIx Master mode, the Disable SCKx pin bit,
DISSCK, may not disable the SPIx clock. As a
result, the PIC
®
microcontroller must provide the
SPIx clock in Master mode.
Work around
None.
Affected Silicon Revisions
41. Module: Output Compare (PWM Mode)
In PWM mode, the output compare module may
miss a compare event when the current duty cycle
register (OCxRS) value is 0x0000 (0% duty cycle)
and the OCxRS register is updated with a value of
0x0001. The compare event is only missed the first
time a value of 0x0001 is written to OCxRS and the
PWM output remains low for one PWM period.
Subsequent PWM high and low times occur as
expected.
Work around
If the current OCxRS register value is 0x0000,
avoid writing a value of 0x0001 to OCxRS.
Instead, write a value of 0x0002. In this case, how-
ever, the duty cycle will be slightly different from
the desired value.
Affected Silicon Revisions
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXXX
X
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX