Information

 2009-2011 Microchip Technology Inc. DS80471B-page 11
PIC24FJ128GA010 FAMILY
30. Module: SPI (Slave Mode)
In SPIx Slave mode (MSTEN = 0), with the slave
select option enabled (SSEN = 1), the peripheral
may accept transfers regardless of the SSx pin
state. The received data in SSPxBUF will be
accurate but not intended for the device.
Work around
If the Slave select option is required (e.g., the
device is one of multiple SPIx slave nodes on an
SPIx network), two potential work arounds exist:
1. Configure the port associated with SSx
to an
input and periodically read the PORT register. If
the pin is read ‘0’, disable the SPIx peripheral
(SPIEN = 0). Enable the peripheral (SPIEN = 1)
if the pin is read as a logic ‘1’.
2. Read the pin associated with SSx
after a trans-
fer is complete, indicated by the SPIxF bit
being set. If the port pin is read as a digital ‘1’,
read SSPxBUF and discard the contents.
Affected Silicon Revisions
31. Module: Oscillator (Two-Speed Start-up)
The Two-Speed Start-up feature may not be
available on exit from Sleep mode with the IESO
bit (Internal External Switchover mode) enabled.
Upon wake-up, the device will wait for the clock
source used prior to entering Sleep mode to
become ready.
Work around
None.
Affected Silicon Revisions
32. Module: Core (Reset)
The CLKDIV register Reset value is incorrect. The
register will reset with unimplemented bits equal to
‘1’ for all Resets.
Work around
Mask out unimplemented bits to maintain software
compatibility with future device revisions.
Affected Silicon Revisions
33. Module: Core (Traps)
If a clock failure occurs when the device is in Idle
mode, the oscillator failure trap does not vector to
the Trap Service Routine (TSR). Instead, the
device will simply wake-up from Idle mode and
continue code execution if the Fail-Safe Clock
Monitor (FSCM) is enabled.
Work around
Whenever the device wakes up from Idle (assuming
the FSCM is enabled), the user software should
check the status of the OSCFAIL bit (INTCON1<1>)
to determine whether a clock failure occurred and
then perform an appropriate clock switch operation.
Affected Silicon Revisions
34. Module: Core (Resets)
On a Brown-out Reset, both the BOR and POR
bits may be set. This may cause the Brown-out
Reset condition to be indistinguishable from the
Power-on Reset.
Work around
None.
Affected Silicon Revisions
35. Module: I/O Ports
During Power-on Reset (POR), the device may
drive the OSCO/CLKO/RC15 pin as a clock out
output for approximately 20 s. During this time,
the pin will be driven high and low rather than
being set to high-impedance. This may cause
issues on designs that use the pin as a general
purpose I/O. Designs should be reviewed to
ensure that their intended operation will not be
disrupted if the pin is driven during POR.
Work around
None.
Affected Silicon Revisions
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX