Information

PIC24FJ128GA010 FAMILY
DS80471B-page 10  2009-2011 Microchip Technology Inc.
25. Module: UART (Auto-Baud)
With the auto-baud feature selected, the Sync
Break character (0x55) may be loaded into the
FIFO as data.
Work around
To prevent the Sync Break character from being
loaded into the FIFO, load the UxBRG register with
either 0x0000 or 0xFFFF prior to enabling the
auto-baud feature (ABAUD = 1).
Affected Silicon Revisions
26. Module: Interrupts (Traps)
The device may not exit Doze mode if certain trap
conditions occur. Address error, stack error and
math error traps are affected. Oscillator failure and
all interrupt sources are not affected and can
cause the device to correctly exit Doze mode.
Work around
None.
Affected Silicon Revisions
27. Module: Output Compare
The output compare module may output a single
glitch for one T
CY after the module is enabled
(OCM<2:0> = 000). This issue occurs when the
output state of the associated Data Latch register
(LATx) is in the opposite state of the Output Com-
pare mode when the peripheral is enabled. It can
also occur when switching between two Output
Compare modes with opposite output states.
Work around
If the output glitch must be avoided, verify that the
associated data latch value of the OCx pin matches
the initial state of the desired Output Compare
mode. For example, if Output Compare 5 is
configured for mode, OCM<2:0> = 001, ensure that
the LATD<4> bit is clear prior to writing the OCM
bits. The port latch output value will match the initial
output state of the OC5 pin and avoid the glitch
when the peripheral is enabled.
Affected Silicon Revisions
28. Module: A/D (INT0 Trigger)
With the External Interrupt 0 (INT0) selected to start
an A/D conversion (SSRC<2:0> = 001), the device
may not wake up from Sleep or Idle mode if more
than one conversion is selected per interrupt
(SMPI<3:0> <> 0000). Interrupts are generated
correctly if the device is not in Sleep or Idle mode.
Work around
Configure the A/D to generate an interrupt after
every conversion (SMPI<3:0> = 0000). Use
another wake-up source, such as the WDT or
another interrupt source, to exit the Sleep or Idle
mode. Alternatively, perform A/D conversions in
Run mode.
Affected Silicon Revisions
29. Module: SPI (Framed Modes)
A frame synchronization pulse may not be output
in SPIx Master mode if the pulse is selected to
coincide with the first bit clock (SPIFE = 1). SCKx
and SDOx waveforms are not affected.
Work around
Select the frame synchronization pulses to
precede the first bit clock (SPIFE = 0). The frame
pulses will output correctly as described in the
product data sheet.
Affected Silicon Revisions
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX
A2 A3 A4 C1 C2
XXX