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ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 100 (14x14) 16-Bit 16 MHz I/O number 84

 2009-2011 Microchip Technology Inc. DS80471B-page 1

PIC24FJ128GA010 FAMILY

The PIC24FJ128GA010 Family devices that you have

received conform functionally to the current Device Data

Sheet (DS39747E), except for the anomalies described

in this document.

The silicon issues discussed in the following pages are

for silicon revisions with the Device and Revision IDs

listed in Table 1. The silicon issues are summarized in

Table 2.

The errata described in this document will be addressed

in future revisions of the PIC24F128GA010 family silicon.

Data Sheet clarifications and corrections start on page 19,

following the discussion of silicon issues.

The silicon revision level can be identified using the

current version of MPLAB

IDE and Microchip’s

programmers, debuggers and emulation tools, which

are available at the Microchip corporate web site

(www.microchip.com).

For example, to identify the silicon revision level using

MPLAB IDE in conjunction with MPLAB ICD 2 or

PICkit™ 3:

1. Using the appropriate interface, connect the

device to the MPLAB ICD 2

programmer/debugger or PICkit™ 3.

2. From the main menu in MPLAB IDE, select

onfigure>Select Device and then select the

target part number in the dialog box.

3. Select the MPLAB hardware tool

(Debugger

>Select Tool).

4. Perform a “Connect” operation to the device

(Debugger

>Connect). Depending on the devel-

opment tool used, the part number and Device

Revision ID value appear in the Output window.

The DEVREV values for the various PIC24F128GA010

family silicon revisions are shown in Table 1.

Note: This document summarizes all silicon

errata issues from all revisions of silicon,

previous as well as current. Only the

issues indicated in the last column of

Table 2 apply to the current silicon revision

(C2).

Note: If you are unable to extract the silicon

revision level, please contact your local

Microchip sales office for assistance.

TABLE 1: SILICON DEVREV VALUES

Part Number Device ID

(1)

Revision ID for Silicon Revision

(2)

A2 A3 A4 C1 C2

PIC24FJ128GA010 040Dh

02h 03h 07h 43h 44h

PIC24FJ96GA010 040Ch

PIC24FJ64GA010 040Bh

PIC24FJ128GA008 040Ah

PIC24FJ96GA008 0409h

PIC24FJ64GA008 0408h

PIC24FJ128GA006 0407h

PIC24FJ96GA006 0406h

PIC24FJ64GA006 0405h

Note 1: The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses in program

memory. They are shown in hexadecimal in the format “DEVID DEVREV”.

2: Refer to the “PIC24FJXXXGA0XX Flash Programming Specification” (DS39768) for detailed information

on Device and Revision IDs for your specific device.

PIC24FJ128GA010 Family

Silicon Errata and Data Sheet Clarification

Summary of content (22 pages)

PAGE 1
PIC24FJ128GA010 FAMILY PIC24FJ128GA010 Family Silicon Errata and Data Sheet Clarification The PIC24FJ128GA010 Family devices that you have received conform functionally to the current Device Data Sheet (DS39747E), except for the anomalies described in this document. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2.
PAGE 2
PIC24FJ128GA010 FAMILY TABLE 2: Module SILICON ISSUE SUMMARY Feature Core Item Number Affected Revisions(1) Issue Summary A2 A3 A4 X X X X X — 1. SFR write issues in Doze mode. I C™ — 2. Failure to lock out writes to I2CxTRN. X UART — 3. Parity failure with odd values in BRG. X Resets — 4. FSCM clock switch issue. X Timers — 5. Special Event Trigger failure (Timer2/3). X 2 SPI Enhanced mode 6. Enhanced Buffer modes are unavailable. X X X JTAG Programming 7.
PAGE 3
PIC24FJ128GA010 FAMILY TABLE 2: Module SILICON ISSUE SUMMARY (CONTINUED) Feature Item Number Affected Revisions(1) Issue Summary A2 A3 A4 SPI Slave mode 30. Module in Slave mode may ignore SSx pin and receive data anyway. X X X Oscillator Two-Speed Start-up 31. Two-Speed Start-up failure when IESO is enabled. X X X Core Reset 32. Unimplemented CLKDIV bits reset to ‘1’. X X X Core Traps 33. Clock failure trap does not vector as expected. X X X Core Resets 34.
PAGE 4
PIC24FJ128GA010 FAMILY TABLE 2: Module SILICON ISSUE SUMMARY (CONTINUED) Feature 2 I C Item Number Affected Revisions(1) Issue Summary A2 A3 A4 X X C1 C2 — 56. TBF flag error with bus collisions. X SPI Master mode 57. Incorrect status bit timing. X RTCC Alarm 58. Pin toggling error on alarm repeat. — 59. Spec change for VOL and VOH. SPI Framed modes 60. Framed SPIx modes are not supported. X X SPI Enhanced mode 61.
PAGE 5
PIC24FJ128GA010 FAMILY 3. Module: UART Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (C2). 1. Module: Core With Doze mode enabled, DOZEN (CLKDIV<11>) set and the CPU Peripheral Clock Ratio Select bits (CLKDIV<14:12>) configured to any value except ‘000’, writes to SFR locations can not be performed.
PAGE 6
PIC24FJ128GA010 FAMILY 5. Module: Timers 8. Module: A/D With Timer2 and Timer3 configured in 32-bit mode by setting T2CON<3>, a Special Event Trigger to start an A/D conversion may not occur when the most significant word of the Period register, PR3, is ‘0’. Work around Either write PR3 to a non-zero value or configure Timer3 for 16-bit operation when generating a Special Event Trigger for periodic A/D conversions.
PAGE 7
PIC24FJ128GA010 FAMILY 10. Module: UART 12. Module: CPU The Receive Buffer Overrun Error Status bit, OERR (UxSTA<1>), may set before the UART FIFO has overflowed. After the fourth byte is received by the UART, the FIFO is full. The OERR bit should set after the fifth byte has been received in the UART Shift register. Instead, the OERR bit may set after the fourth received byte with the UART Shift register empty.
PAGE 8
PIC24FJ128GA010 FAMILY 14. Module: PMP (Master Mode) With the PMP in Master mode (MODE<1:0> = 11 or 10) with the increment/decrement feature enabled (INCM<1:0> = 01 or 10), the address may not automatically change when the PMDINx register is read. This issue may occur when multiple back-to-back reads are performed. Work around The PMP address will be generated correctly if a minimum of one instruction cycle delay is inserted between the back-to-back read operations of the PMDINx register.
PAGE 9
PIC24FJ128GA010 FAMILY 19. Module: UART 22. Module: UART The timing for transmitting a Sync Break has changed for this revision of silicon. The Sync Break is transmitted as soon as the UTXBRK bit is set. A dummy write to UxTXREG is still required and must be performed before the Sync Break has finished transmitting. Otherwise, the UxTX may be held in the active state until the write has occurred.
PAGE 10
PIC24FJ128GA010 FAMILY 25. Module: UART (Auto-Baud) With the auto-baud feature selected, the Sync Break character (0x55) may be loaded into the FIFO as data. Work around To prevent the Sync Break character from being loaded into the FIFO, load the UxBRG register with either 0x0000 or 0xFFFF prior to enabling the auto-baud feature (ABAUD = 1). Affected Silicon Revisions A2 A3 A4 X X X C1 C2 28.
PAGE 11
PIC24FJ128GA010 FAMILY 30. Module: SPI (Slave Mode) In SPIx Slave mode (MSTEN = 0), with the slave select option enabled (SSEN = 1), the peripheral may accept transfers regardless of the SSx pin state. The received data in SSPxBUF will be accurate but not intended for the device. Work around If the Slave select option is required (e.g., the device is one of multiple SPIx slave nodes on an SPIx network), two potential work arounds exist: 1.
PAGE 12
PIC24FJ128GA010 FAMILY 36. Module: I2C (Slave Mode) During I2C Slave mode transactions, the Data/Address bit, D/A, may not update during the data frame. This affects both 7 and 10-Bit Addressing modes. 39. Module: UART I2C slave receptions are not affected by this issue. When the UART uses two Stop bits (STSEL = 1), it may sample the first Stop bit instead of the second one. If the device being communicated with is using one Stop bit in its communications, this may lead to framing errors.
PAGE 13
PIC24FJ128GA010 FAMILY 45. Module: I2C 42. Module: CRC If a CRC FIFO overflow occurs, the VWORD indicator will reset to ‘1’ instead of ‘0’. Further writes to the FIFO will cause the VWORD indicator to reset to ‘0’ after seven writes are performed. After the ACKSTAT bit is set, while receiving a NACK from the master or a slave, it may be cleared by the reception of a Start or Stop bit. Work around Store the value of the ACKSTAT bit immediately after receiving a NACK.
PAGE 14
PIC24FJ128GA010 FAMILY 47. Module: Core (Instruction Set) 49. Module: I/O (PORTB) If an instruction producing a read-after-write stall condition is executed inside a REPEAT loop, the instruction will be executed fewer times than was intended. For example, this loop: When RB5 is configured as an open-drain output, it remains in a high-impedance state. The settings of LATB5 and TRISB5 have no effect on the pin’s state. repeat #0xf inc [w1],[++w1] Work around will execute less than 15 times.
PAGE 15
PIC24FJ128GA010 FAMILY 51. Module: UART (UERIF Interrupt) The UART error interrupt may not occur, or occur at an incorrect time, if multiple errors occur during a short period of time. Work around Read the error flags in the UxSTA register whenever a byte is received to verify the error status. In most cases, these bits will be correct, even if the UART error interrupt fails to occur. For possible exceptions, refer to Errata # 52. Affected Silicon Revisions A2 A3 A4 X X X C1 C2 54.
PAGE 16
PIC24FJ128GA010 FAMILY 56. Module: I2C 57. Module: SPI (Master Mode) The Transmit Buffer Full (TBF) flag (I2CxSTAT<0>) may not be cleared by hardware if a collision on the I2C bus occurs before the first falling clock edge during a transmission. Work around None. Affected Silicon Revisions A2 A3 A4 X X X C1 C2 In Master mode, the SPIx Interrupt Flag (SPIxIF) and the SPIRBF bit (SPIxSTAT<0>) may both become set one-half clock cycle early, instead of on the clock edge.
PAGE 17
PIC24FJ128GA010 FAMILY 58. Module: RTCC (Alarm) 59. Module: I/O Pins The RTCC alarm repeat will generate an incorrect number of pin toggles. If the repeat count (x) is even, it will toggle the alarm pin ‘x’ times. If the repeat count is odd, one less than x toggles will be observed (x – 1). The I/O pin output, VOL, meets the specifications in Table 3 below. Work around Affected Silicon Revisions Work around None. None at this time.
PAGE 18
PIC24FJ128GA010 FAMILY 60. Module: SPI (Framed SPIx Modes) Framed SPIx modes, as described in the device data sheet, are not supported. When using the module, verify the FRMEN bit (SPIxCON2<15>) is cleared. 62. Module: Core (Code Protection) None. When general segment code protection has been enabled (GCP Configuration bit is programmed), applications are unable to write to the first 512 bytes of the program memory space (0000h through 0200h).
PAGE 19
PIC24FJ128GA010 FAMILY Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS39747E): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. None.  2009-2011 Microchip Technology Inc.
PAGE 20
PIC24FJ128GA010 FAMILY APPENDIX A: DOCUMENT REVISION HISTORY Rev A Document (6/2009) Initial release of this document; issued for revision C2.
PAGE 21
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PAGE 22
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