Datasheet

 2010 Microchip Technology Inc. DS39969B-page 89

PIC24FJ256DA210 FAMILY

TABLE 6-1: RESET FLAG BIT OPERATION

bit 2 IDLE: Wake-up From Idle Flag bit

1 = Device has been in Idle mode

0 = Device has not been in Idle mode

bit 1 BOR: Brown-out Reset Flag bit

1 = A Brown-out Reset has occurred

Note that BOR is also set after a Power-on Reset.

0 = A Brown-out Reset has not occurred

bit 0 POR: Power-on Reset Flag bit

1 = A Power-on Reset has occurred

0 = A Power-on Reset has not occurred

(1)

(CONTINUED)

Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the

SWDTEN bit setting.

3: Re-enabling the regulator after it enters Standby mode will add a delay, T

VREG, when waking up from

Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from

occurring.

Flag Bit Setting Event Clearing Event

TRAPR (RCON<15>) Trap Conflict Event POR

IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR

CM (RCON<9>) Configuration Mismatch Reset POR

EXTR (RCON<7>) MCLR

Reset POR

SWR (RCON<6>) RESET Instruction POR

WDTO (RCON<4>) WDT Time-out CLRWDT, PWRSAV

Instruction, POR

SLEEP (RCON<3>) PWRSAV #0 Instruction POR

IDLE (RCON<2>) PWRSAV #1 Instruction POR

BOR (RCON<1>) POR, BOR —

POR (RCON<0>) POR —

Note: All Reset flag bits may be set or cleared by the user software.