Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 88  2010 Microchip Technology Inc.
REGISTER 6-1: RCON: RESET CONTROL REGISTER
(1)
R/W-0, HS R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS R/W-0
TRAPR IOPUWR — — — —CMVREGS
(3)
bit 15 bit 8
R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS
EXTR SWR SWDTEN
(2)
WDTO SLEEP IDLE BOR POR
bit 7 bit 0
Legend: HS = Hardware Settable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 TRAPR: Trap Reset Flag bit
1 = A Trap Conflict Reset has occurred
0 = A Trap Conflict Reset has not occurred
bit 14 IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1 = An illegal opcode detection, an illegal address mode or uninitialized W register is used as an
Address Pointer and caused a Reset
0 = An illegal opcode or uninitialized W Reset has not occurred
bit 13-10 Unimplemented: Read as ‘0’
bit 9 CM: Configuration Word Mismatch Reset Flag bit
1 = A Configuration Word Mismatch Reset has occurred
0 = A Configuration Word Mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Standby Enable bit
(3)
1 = Program memory and regulator remain active during Sleep/Idle
0 = Program memory power is removed and regulator goes to standby during Seep/Idle
bit 7 EXTR: External Reset (MCLR
) Pin bit
1 = A Master Clear (pin) Reset has occurred
0 = A Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset (Instruction) Flag bit
1 =A RESET instruction has been executed
0 =A RESET instruction has not been executed
bit 5 SWDTEN: Software Enable/Disable of WDT bit
(2)
1 = WDT is enabled
0 = WDT is disabled
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT time-out has occurred
0 = WDT time-out has not occurred
bit 3 SLEEP: Wake From Sleep Flag bit
1 = Device has been in Sleep mode
0 = Device has not been in Sleep mode
Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
3: Re-enabling the regulator after it enters Standby mode will add a delay, T
VREG, when waking up from
Sleep. Applications that do not use the voltage regulator should set this bit to prevent this delay from
occurring.