Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TFBGA 121 (10x10) 16-Bit 32 MHz I/O number 84

 2010 Microchip Technology Inc. DS39969B-page 69

PIC24FJ256DA210 FAMILY

TABLE 4-31: GRAPHICS REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

G1CMDL 0700 Graphics Command Register<15:0>

0000

G1CMDH 0702 Graphics Command Register<31:16>

0000

G1CON1 0704 G1EN — G1SIDL GCMDWMK4 GCMDWMK3 GCMDWMK2

GCMDWMK1 GCMDWMK0 PUBPP2 PUBPP1 PUBPP0 GCMDCNT4 GCMDCNT3 GCMDCNT2 GCMDCNT1 GCMDCNT0

0000

G1STAT 0706 PUBUSY — — — — — — — IPUBUSY RCCBUSY CHRBUSY VMRGN HMRGN CMDLV CMDFUL CMDMPT

0000

G1IE 0708 PUIE — — — — — — — IPUIE RCCIE CHRIE VMRGNIE HMRGNIE CMDLVIE CMDFULIE CMDMPTIE

0000

G1IR 070A PUIF — — — — — — — IPUIF RCCIF CHRIF VMRGNIF HMRGNIF CMDLVIF CMDFULIF CMDMPTIF

0000

G1W1ADRL 070C GPU Work Area 1 Start Address Register<15:0>

0000

G1W1ADRH 070E — — — — — — — — GPU Work Area 1 Start Address Register<23:16>

0000

G1W2ADRL 0710 GPU Work Area 2 Start Address Register<15:0>

0000

G1W2ADRH 0712 — — — — — — — — GPU Work Area 2 Start Address Register<23:16>

0000

G1PUW 0714 — — — — — GPU Work Area Width Register

0000

G1PUH 0716 — — — — — GPU Work Area Height Register

0000

G1DPADRL 0718 Display Buffer Start Address Register<15:0>

0000

G1DPADRH 071A — — — — — — — — Display Buffer Start Address Register<23:16>

0000

G1DPW 071C — — — — — Display Frame Width Register

0000

G1DPH 071E — — — — — Display Frame Height Register

0000

G1DPWT 0720 — — — — — Display Total Width Register

0000

G1DPHT 0722 — — — — — Display Total Height Register

0000

G1CON2 0724 DPGWDTH1 DPGWDTH0 DPSTGER1 DPSTGER0 — — DPTEST1 DPTEST0 DPBPP2 DPBPP1 DPBPP0 — — DPMODE2 DPMODE1 DPMODE0

0000

G1CON3 0726 — — — — — — DPPINOE DPPOWER DPCLKPOL DPENPOL DPVSPOL DPHSPOL DPPWROE DPENOE DPVSOE DPHSOE

0000

G1ACTDA 0728 Number of Lines Before the First Active Line Register Number of Pixels Before the First Active PIxel Register

0000

G1HSYNC 072A HSYNC Pulse-Width Configuration Register HSYNC Start Delay Configuration Register

0000

G1VSYNC 072C VSYNC Pulse-Width Configuration Register VSYNC Start Delay Configuration Register

0000

G1DBLCON 072E Vertical Blanking Start to First Displayed Line Configuration Regsiter Horizontal Blanking Start to First Displayed Line Configuration Regsiter

0000

G1CLUT 0730 CLUTEN CLUTBUSY — — — — CLUTTRD CLUTRWEN Color Look-Up Table Memory Address Register

0000

G1CLUTWR 0732 Color Look-up Table Memory Write Data Register

0000

G1CLUTRD 0734 Color Look-up Table Memory Read Data Register

0000

G1MRGN 0736 Vertical Blanking Advance Register Horizontal Blanking Advance Register

0000

G1CHRX 0738

— — — — — Current Character X-Coordinate Position Register

0000

G1CHRY 073A

— — — — — Current Character Y-Coordinate Position Register

0000

G1IPU 073C

— — — — — — — — — — HUFFERR BLCKERR LENERR WRAPERR IPUDONE BFINAL

0000

G1DBEN 073E GDBEN15 GDBEN14 GDBEN13 GDBEN12 GDBEN11 GDBEN10 GDBEN9 GDBEN8 GDBEN7 GDBEN6 GDBEN5 GDBEN4 GDBEN3 GDBEN2 GDBEN1 GDBEN0

0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.