Datasheet

PIC24FJ256DA210 FAMILY

DS39969B-page 50  2010 Microchip Technology Inc.

TABLE 4-4: CPU CORE REGISTERS MAP

File

Name

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

WREG0 0000 Working Register 0 0000

WREG1 0002 Working Register 1 0000

WREG2 0004 Working Register 2 0000

WREG3 0006 Working Register 3 0000

WREG4 0008 Working Register 4 0000

WREG5 000A Working Register 5 0000

WREG6 000C Working Register 6 0000

WREG7 000E Working Register 7 0000

WREG8 0010 Working Register 8 0000

WREG9 0012 Working Register 9 0000

WREG10 0014 Working Register 10 0000

WREG11 0016 Working Register 11 0000

WREG12 0018 Working Register 12 0000

WREG13 001A Working Register 13 0000

WREG14 001C Working Register 14 0000

WREG15 001E Working Register 15 0800

SPLIM 0020 Stack Pointer Limit Value Register xxxx

PCL 002E Program Counter Low Word Register 0000

PCH 0030

— — — — — — — — Program Counter Register High Byte 0000

DSRPAG 0032

— — — — — — Extended Data Space Read Page Address Register 0001

DSWPAG

(1)

0034 — — — — — — — Extended Data Space Write Page Address Register 0001

RCOUNT 0036 Repeat Loop Counter Register xxxx

SR 0042

— — — — — — — DC IPL2 IPL1 IPL0 RA N OV Z C 0000

CORCON 0044

— — — — — — — — — — — —IPL3 r — — 0004

DISICNT 0052

— — Disable Interrupts Counter Register xxxx

TBLPAG 0054

— — — — — — — — Table Memory Page Address Register 0000

Legend: — = unimplemented, read as ‘0’; r = Reserved bit. Reset values are shown in hexadecimal.

Note 1: Reserved in PIC24FJXXXDA106 devices; do not use.