Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 40  2010 Microchip Technology Inc.
FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM
TABLE 3-1: CPU CORE REGISTERS
Register(s) Name Description
W0 through W15 Working Register Array
PC 23-Bit Program Counter
SR ALU STATUS Register
SPLIM Stack Pointer Limit Value Register
TBLPAG Table Memory Page Address Register
RCOUNT Repeat Loop Counter Register
CORCON CPU Control Register
DISICNT Disable Interrupt Count Register
DSRPAG Data Space Read Page Register
DSWPAG Data Space Write Page Register
Instruction
Decode and
Control
PCH PCL
16
Program Counter
16-Bit ALU
23
23
24
23
Data Bus
Instruction Reg
16
16 x 16
W Register Array
Divide
Support
ROM Latch
16
EA MUX
RAGU
WAGU
16
16
8
Interrupt
Controller
EDS and Table
Data Access
Control Block
Stack
Control
Logic
Loop
Control
Logic
Data Latch
Data RAM
Address
Latch
Control Signals
to Various Blocks
Program Memory/
Data Latch
Address Bus
16
Literal Data
16
16
Hardware
Multiplier
16
To Peripheral Modules
Address Latch
Up to 0x7FFF
Extended Data
Space