Datasheet
2010 Microchip Technology Inc. DS39969B-page 381
PIC24FJ256DA210 FAMILY
TABLE 30-13: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated)
Operating temperature -40°C T
A +85°C for Industrial
Param
No.
Symbol Characteristic Min Typ
(1)
Max Units Conditions
OS10 F
OSC External CLKI Frequency
(External clocks allowed
only in EC mode)
DC
4
—
—
32
48
MHz
MHz
EC
ECPLL
Oscillator Frequency 3.5
4
10
10
31
—
—
—
—
—
10
8
32
32
33
MHz
MHz
MHz
MHz
kHz
XT
XTPLL
HS
HSPLL
SOSC
OS20 TOSC TOSC = 1/FOSC — — — — See parameter OS10 for
F
OSC value
OS25 T
CY Instruction Cycle Time
(2)
62.5 — DC ns
OS30 TosL,
TosH
External Clock in (OSCI)
High or Low Time
0.45 x T
OSC ——nsEC
OS31 TosR,
TosF
External Clock in (OSCI)
Rise or Fall Time
— — 20 ns EC
OS40 TckR CLKO Rise Time
(3)
— 6 10 ns
OS41 TckF CLKO Fall Time
(3)
— 6 10 ns
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: Instruction cycle period (T
CY) equals two times the input oscillator time base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an
external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time
limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the
Q1-Q2 period (1/2 T
CY) and high for the Q3-Q4 period (1/2 TCY).
TABLE 30-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.2V TO 3.6V)
AC CHARACTERISTICS
Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated)
Operating temperature -40°C T
A +85°C for Industrial
Param
No.
Symbol Characteristic
(1)
Min Typ
(2)
Max Units Conditions
OS50 F
PLLI PLL Input Frequency
Range
(2)
4 — 48 MHz ECPLL mode
432MHzHSPLL mode
4 8 MHz XTPLL mode
OS51 F
SYS PLL Output Frequency
Range
95.76 — 96.24 MHz
OS52 T
LOCK PLL Start-up Time
(Lock Time)
——200s
OS53 D
CLK CLKO Stability (Jitter) -0.25 — 0.25 %
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.