Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 354  2010 Microchip Technology Inc.
27.2 On-Chip Voltage Regulator
All PIC24FJ256DA210 family devices power their core
digital logic at a nominal 1.8V. This may create an issue
for designs that are required to operate at a higher
typical voltage, such as 3.3V. To simplify system
design, all devices in the PIC24FJ256DA210 family
incorporate an on-chip regulator that allows the device
to run its core logic from V
DD.
The regulator is controlled by the ENVREG pin. Tying V DD
to the pin enables the regulator, which in turn, provides
power to the core from the other V
DD pins. When the reg-
ulator is enabled, a low-ESR capacitor (such as ceramic)
must be connected to the V
CAP pin (Figure 27-1). This
helps to maintain the stability of the regulator. The recom-
mended value for the filter capacitor (C EFC ) is provided in
Section 30.1 “DC Characteristics” .
27.2.1 VOLTAGE REGULATOR
LOW-VOLTAGE DETECTION
When the on-chip regulator is enabled, it provides a
constant voltage of 1.8V nominal to the digital core
logic.
The regulator can provide this level from a V
DD of about
2.1V, all the way up to the device’s V
DDMAX. It does not
have the capability to boost V
DD levels. In order to pre-
vent “brown-out” conditions when the voltage drops too
low for the regulator, the Brown-out Reset occurs. Then
the regulator output follows V
DD with a typical voltage
drop of 300 mV.
To provide information about when the regulator
voltage starts reducing, the on-chip regulator includes
a simple Low-Voltage Detect circuit, which sets the
Low-Voltage Detect Interrupt Flag, LVDIF (IFS4<8>).
This can be used to generate an interrupt to trigger an
orderly shutdown.
FIGURE 27-1: CONNECTIONS FOR THE
ON-CHIP REGULATOR
27.2.2 ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approx-
imately 10 s for it to generate output. During this time,
designated as T
VREG, code execution is disabled.
T
VREG is applied every time the device resumes
operation after any power-down, including Sleep mode.
T
VREG is determined by the status of the VREGS bit
(RCON<8>) and the WUTSEL Configuration bits
(CW3<11:10>). Refer to Section 30.0 “Electrical
Characteristics” for more information on T
VREG.
REGISTER 27-6: DEVREV: DEVICE REVISION REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 23 bit 16
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 R R R R
— — — — REV3 REV2 REV1 REV0
bit 7 bit 0
Legend: R = Readable bit U = Unimplemented bit
bit 23-4 Unimplemented: Read as ‘0’
bit 3-0 REV<3:0>: Device revision identifier bits
VDD
ENVREG
V
CAP
VSS
PIC24FJXXXDA1/DA2
CEFC
3.3V
(1)
Regulator Enabled (ENVREG tied to VDD):
Note 1: This is a typical operating voltage. Refer to
Section 30.1 “DC Characteristics” for
the full operating ranges of V
DD.
(10 F typ)