Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 332  2010 Microchip Technology Inc.
EQUATION 23-1: A/D CONVERSION CLOCK PERIOD
(1)
REGISTER 23-7: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH)
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — CSSL27 CSSL26 CSSL25 CSSL24
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL23
(1)
CSSL22
(1)
CSSL21
(1)
CSSL20
(1)
CSSL19
(1)
CSSL18
(1)
CSSL17
(1)
CSSL16
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-12 Unimplemented: Read as ‘0’
bit 11 CSSL27: A/D Input Band Gap Scan Selection bit
1 = Band gap divided-by-six reference (V
BG/6) is selected for input scan
0 = Analog channel is omitted from input scan
bit 10 CSSL26: A/D Input Band Gap Scan Selection bit
1 = Internal core voltage (V
CAP) is selected for input scan
0 = Analog channel is omitted from input scan
bit 9 CSSL25: A/D Input Half Band Gap Scan Selection bit
1 = Band gap reference (V
BG) is selected for input scan
0 = Analog channel is omitted from input scan
bit 8 CSSL24: A/D Input Band Gap Scan Selection bit
1 = Band gap divided-by-two reference (V
BG/2) is selected for input scan
0 = Analog channel is omitted from input scan
bit 7-0 CSSL<23:16>: Analog Input Pin Scan Selection bits
(1)
1 = Corresponding analog channel selected for input scan
0 = Analog channel is omitted from input scan
Note 1: Unimplemented in 64-pin devices, read as ‘0’.
Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
ADCS =
T
AD
TCY
– 1
TAD = TCY • (ADCS = 1)