Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 318  2010 Microchip Technology Inc.
REGISTER 22-23: G1VSYNC: VERTICAL SYNCHRONIZATION CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VSLEN7 VSLEN6 VSLEN5 VSLEN4 VSLEN3 VSLEN2 VSLEN1 VSLEN0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VSST7 VSST6 VSST5 VSST4 VSST3 VSST2 VSST1 VSST0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 VSLEN<7:0>: V
SYNC Pulse-Width Configuration bits (in lines)
The DPVSOE bit (G1CON3<1>) must be set for the V
SYNC signal to toggle; minimum value is 1.
bit 7-0 VSST<7:0>: V
SYNC Start Delay Configuration bits (in lines)
This is the number of lines from the start of vertical blanking to the start of V
SYNC active.
REGISTER 22-24: G1DBLCON: DISPLAY BLANKING CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
VENST7 VENST6 VENST5 VENST4 VENST3 VENST2 VENST1 VENST0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
HENST7 HENST6 HENST5 HENST4 HENST3 HENST2 HENST1 HENST0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 VENST<7:0>: Vertical Blanking Start to First Displayed Line Configuration bits (in lines)
This is the number of lines from the start of vertical blanking to the first displayed line of a frame.
bit 7-0 HENST<7:0>: Horizontal Blanking Start to First Displayed Pixel Configuration bits (in DISPCLKs)
This is the number of GCLK cycles from the start of horizontal blanking to the first displayed pixel of
each displayed line.