Datasheet

 2010 Microchip Technology Inc. DS39969B-page 313
PIC24FJ256DA210 FAMILY
REGISTER 22-9: G1W1ADRL: GPU WORK AREA 1 START ADDRESS REGISTER LOW
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W1ADR15 W1ADR14 W1ADR13 W1ADR12 W1ADR11 W1ADR10 W1ADR9 W1ADR8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W1ADR7 W1ADR6 W1ADR5 W1ADR4 W1ADR3 W1ADR2 W1ADR1 W1ADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 W1ADR<15:0>: GPU Work Area 1 Start Address Low bits
Work area address must point to an even byte address in memory.
REGISTER 22-10: G1W1ADRH: GPU WORK AREA 1 START ADDRESS REGISTER HIGH
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W1ADR23 W1ADR22 W1ADR21 W1ADR20 W1ADR19 W1ADR18 W1ADR17 W1ADR16
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 W1ADR<23:16>: GPU Work Area 1 Start Address High bits
Work area address must point to an even byte address in memory.
REGISTER 22-11: G1W2ADRL: GPU WORK AREA 2 START ADDRESS REGISTER LOW
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W2ADR15 W2ADR14 W2ADR13 W2ADR12 W2ADR11 W2ADR10 W2ADR9 W2ADR8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
W2ADR7 W2ADR6 W2ADR5 W2ADR4 W2ADR3 W2ADR2 W2ADR1 W2ADR0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-0 W2ADR<15:0>: GPU Work Area 2 Start Address Low bits
Work area address must point to an even byte address in memory.