Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 308  2010 Microchip Technology Inc.
REGISTER 22-4: G1CON2: DISPLAY CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
DPGWDTH1 DPGWDTH0 DPSTGER1 DPSTGER0
— — DPTEST1 DPTEST0
bit 15 bit 8
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
DPBPP2 DPBPP1 DPBPP0
— — DPMODE2 DPMODE1 DPMODE0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-14 DPGWDTH<1:0>: STN Display Glass Data Width bits
11 = Reserved
10 = 16 bits wide
01 = 8 bits wide
00 = 4 bits wide
These bits have no effect on TFT mode. TFT display glass data width is always assumed to be 16 bits wide.
bit 13-12 DPSTGER<1:0>: Display Data Timing Stagger bits
11 = Delays of the display data are staggered in groups:
Bit group 0: 0 4 8 12 – not delayed
Bit group 1: 1 5 9 13 – delayed by ½ GPUCLK cycle
Bit group 2: 2 6 10 14 – delayed by full GPUCLK cycle
Bit group 3: 3 7 11 15 – delayed by 1 ½ GPUCLK cycle
10 = Even bits of the display data are delayed by 1 full GPUCLK cycle; odd bits are not delayed
01 = Odd bits of the display data are delayed by ½ GPUCLK cycle; even bits are not delayed
00 = Display data timing is all synchronized on one clock GPUCLK edge
bit 11-10 Unimplemented: Read as ‘0’
bit 9-8 DPTEST<1:0>: Display Test Pattern Generator bits
11 = Borders
10 = Bars
01 = Black screen
00 = Normal Display mode; test patterns are off
bit 7-5 DPBPP<2:0>: Display bits-per-pixel Setting bits
This setting must match the GPU bits-per-pixel set in PUBPP<2:0> (G1CON1<7:5>).
100 = 16 bits-per-pixel
011 = 8 bits-per-pixel
010 = 4 bits-per-pixel
001 = 2 bits-per-pixel
000 = 1 bit-per-pixel
Other = Reserved
bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 DPMODE<2:0>: Display Glass Type bits
011 = Color STN type
010 = Mono STN type
001 = TFT type
000 = Display off
Other = Reserved