Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 264  2010 Microchip Technology Inc.
18.7.2 USB INTERRUPT REGISTERS
REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS U-0 R/K-0, HS
IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF
— VBUSVDIF
bit 7 bit 0
Legend: U = Unimplemented bit, read as ‘0’
R = Readable bit K = Write ‘1’ to clear bit HS = Hardware Settable bit
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-8 Unimplemented: Read as ‘0’
bit 7 IDIF: ID State Change Indicator bit
1 = Change in ID state is detected
0 = No ID state change is detected
bit 6 T1MSECIF: 1 Millisecond Timer bit
1 = The 1 millisecond timer has expired
0 = The 1 millisecond timer has not expired
bit 5 LSTATEIF: Line State Stable Indicator bit
1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different from
the last time
0 = USB line state has not been stable for 1 ms
bit 4 ACTVIF: Bus Activity Indicator bit
1 = Activity on the D+/D- lines or V
BUS is detected
0 = No activity on the D+/D- lines or V
BUS is detected
bit 3 SESVDIF: Session Valid Change Indicator bit
1 =VBUS has crossed VA_SESS_END (as defined in the USB OTG Specification)
(1)
0 =VBUS has not crossed VA_SESS_END
bit 2 SESENDIF: B-Device VBUS Change Indicator bit
1 =V
BUS change on B-device detected; VBUS has crossed VB_SESS_END (as defined in the USB
OTG Specification)
(1)
0 =VBUS has not crossed VA_SESS_END
bit 1 Unimplemented: Read as ‘0’
bit 0 VBUSVDIF: A-Device V
BUS Change Indicator bit
1 =V
BUS change on A-device is detected; VBUS has crossed VA_VBUS_VLD (as defined in the USB
OTG Specification)
(1)
0 =No VBUS change on A-device is detected
Note 1: V
BUS threshold crossings may be either rising or falling.
Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.