Datasheet

 2010 Microchip Technology Inc. DS39969B-page 207
PIC24FJ256DA210 FAMILY
bit 3 TRIGMODE: Trigger Status Mode Select bit
1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0 = TRIGSTAT is only cleared by software
bit 2-0 OCM<2:0>: Output Compare x Mode Select bits
(1)
111 = Center-Aligned PWM mode on OCx
(2)
110 = Edge-Aligned PWM Mode on OCx
(2)
101 = Double Compare Continuous Pulse mode: Initialize the OCx pin low, the toggle OCx state
continuously on alternate matches of OCxR and OCxRS
100 = Double Compare Single-Shot mode: Initialize the OCx pin low, toggle the OCx state on matches
of OCxR and OCxRS for one cycle
011 = Single Compare Continuous Pulse mode: Compare events continuously toggle the OCx pin
010 = Single Compare Single-Shot mode: Initialize OCx pin high, compare event forces the OCx pin low
001 = Single Compare Single-Shot mode: Initialize OCx pin low, compare event forces the OCx pin high
000 = Output compare channel is disabled
REGISTER 14-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
Note 1: The OCx output must also be configured to an available RPn pin. For more information, see Section 10.4
“Peripheral Pin Select (PPS)”.
2: The Fault input enable and Fault status bits are valid when OCM<2:0> = 111 or 110.
3: The Comparator 1 output controls the OC1-OC3 channels; Comparator 2 output controls the OC4-OC6
channels; Comparator 3 output controls the OC7-OC9 channels.
4: The OCFA/OCFB Fault input must also be configured to an available RPn/RPIn pin. For more information,
see Section 10.4 “Peripheral Pin Select (PPS)”.