Datasheet

 2010 Microchip Technology Inc. DS39969B-page 147
PIC24FJ256DA210 FAMILY
REGISTER 8-4: CLKDIV2: CLOCK DIVIDER REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
GCLKDIV6
(1)
GCLKDIV5
(1)
GCLKDIV4
(1)
GCLKDIV3
(1)
GCLKDIV2
(1)
GCLKDIV1
(1)
GCLKDIV0
(1)
—
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at all Resets ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 GCLKDIV<6:0>: Display Module Interface Clock Divider Selection bits
(1)
(Values are based on a 96 MHz clock source set by G1CLKSEL (CLKDIV<4>) = 1. When the 48 MHz
clock source is selected, G1CLKSEL (CLKDIV<4>) = 0; all values are divided by 2.)
(1)
1111111 = (127) 1.50 MHz (divide by 64)
1111110 = (126) 1.52 MHz (divide by 63)
·
·
·
1100001 = (97) 2.82 MHz (divide by 34)
1100000 = (96) 2.91 MHz (divide by 33); from here, increment the divisor by 1.00
1011111 = (95) 2.95 MHz (divide by 32.50)
·
·
·
1000000 = (65) 5.49 MHz (divide by 17.50)
1000000 = (64) 5.65 MHz (divide by 17.00); from here, increment the divisor by 0.50
0111111 = (63) 5.73 MHz (divide by 16.75)
·
·
·
0000011 = (3) 54.86 MHz (divide by 1.75)
0000010 = (2) 64.00 MHz (divide by 1.5)
0000001 = (1) 76.80 MHz (divide by 1.25); from here, increment the divisor by 0.25
0000000 = (0) 96.00 MHz (divide by 1)
bit 8-0 Unimplemented: Read as ‘0’
Note 1: These bits take effect only when the 96 MHz PLL is enabled.