Datasheet

PIC24FJ256DA210 FAMILY
DS39969B-page 142  2010 Microchip Technology Inc.
8.1 CPU Clocking Scheme
The system clock source can be provided by one of
four sources:
• Primary Oscillator (POSC) on the OSCI and
OSCO pins
• Secondary Oscillator (SOSC) on the SOSCI and
SOSCO pins
• Fast Internal RC (FRC) Oscillator
• Low-Power Internal RC (LPRC) Oscillator
The primary oscillator and FRC sources have the
option of using the internal 24x PLL block, which
generates the USB module clock, the Graphics module
clock and a separate system clock through the 96 MHZ
PLL. Refer to Section 8.5 “96 MHz PLL Block” for
additional information.
The internal FRC provides an 8 MHz clock source. It
can optionally be reduced by the programmable clock
divider to provide a range of system clock frequencies.
The selected clock source generates the processor
and peripheral clock sources. The processor clock
source is divided by two to produce the internal instruc-
tion cycle clock, F
CY. In this document, the instruction
cycle clock is also denoted by F
OSC/2. The internal
instruction cycle clock, F
OSC/2, can be provided on the
OSCO I/O pin for some operating modes of the primary
oscillator.
8.2 Initial Configuration on POR
The oscillator source (and operating mode) that is used
at a device Power-on Reset (POR) event is selected
using Configuration bit settings. The oscillator Configu-
ration bit settings are located in the Configuration
registers in the program memory (refer to Section 27.1
“Configuration Bits” for further details). The Primary
Oscillator Configuration bits, POSCMD<1:0> (Configu-
ration Word 2<1:0>) and the Initial Oscillator Select
Configuration bits, FNOSC<2:0> (Configuration
Word 2<10:8>), select the oscillator source that is used
at a POR. The FRC primary oscillator with postscaler
(FRCDIV) is the default (unprogrammed) selection. The
secondary oscillator, or one of the internal oscillators,
may be chosen by programming these bit locations.
The Configuration bits allow users to choose between
the various clock modes, shown in Table 8-1.
8.2.1 CLOCK SWITCHING MODE
CONFIGURATION BITS
The FCKSM Configuration bits (Configuration
Word 2<7:6>) are used to jointly configure device clock
switching and the Fail-Safe Clock Monitor (FSCM).
Clock switching is enabled only when FCKSM1 is
programmed (‘0’). The FSCM is enabled only when
FCKSM<1:0> are both programmed (‘00’).
TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0> Notes
Fast RC Oscillator with Postscaler
(FRCDIV)
Internal 11 111 1, 2
FRC Oscillator/16 (500 KHz) Internal 11 110 1
Low-Power RC Oscillator (LPRC) Internal 11 101 1
Secondary (Timer1) Oscillator
(SOSC)
Secondary 11 100 1
Primary Oscillator (XT) with PLL
Module (XTPLL)
Primary 01 011 —
Primary Oscillator (EC) with PLL
Module (ECPLL)
Primary 00 011 1
Primary Oscillator (HS) Primary 10 010 —
Primary Oscillator (XT) Primary 01 010 —
Primary Oscillator (EC) Primary 00 010 1
Fast RC Oscillator with PLL Module
(FRCPLL)
Internal 11 001 1
Fast RC Oscillator (FRC) Internal 11 000 1
Note 1: OSCO pin function is determined by the OSCIOFCN Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.