Information

 2011-2013 Microchip Technology Inc. DS80000534C-page 3
PIC24F16KL402 FAMILY
Silicon Errata Issues
1. Module: UART (Transmit)
The Transmit Buffer Full Flag, UTXBF
(UxSTA<9>), may become cleared before data
starts moving out of the full buffer. If the flag is
used to determine when data can be written to
the buffer, new data may not be accepted, and
data may not be transmitted.
Work around
Poll the Transmit Buffer Empty Flag (TRMT,
UxSTA<8>) to determine when the transmit
buffer is empty and can be written to.
Alternatively, configure the UART to set the
Transmit Interrupt Flag (UxTXIF) whenever a
character is shifted into the Transmit Shift Reg-
ister (UTXISEL<1:0> = 00). When a transmit
interrupt occurs, this indicates that at least one
buffer position is open and that the buffer can be
written to.
Affected Silicon Revisions
2. Module: Oscillator (REFO)
When output frequencies above 16 MHz are
selected for the Reference Clock Output
(REFO), the peak output voltage on the REFO
pin may be too low to be properly detected by
external devices.
Work around
None.
Affected Silicon Revisions
3. Module: HLVD (Band Gap Reference)
At the extreme low end of the operating tem-
perature range (near -40°C), the BGVST and
IRVST flag bits (HLVDCON<6,5>) may not
become set when the voltage references are
stable and ready to use.
Work around
For applications that run at extremely cold tem-
peratures, do not use the BGVST and IRVST
bits as the sole indicator of band gap readiness.
Include a time-out of 750 µs between enabling
and using a reference.
Affected Silicon Revisions
Note: This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A1).
A0 A1
X
A0 A1
X
X
A0
A1
X
X