Datasheet

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DS39995D-page 49  2011-2013 Microchip Technology Inc.

TABLE 4-21: CRC REGISTER MAP

File

Name

Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

CRCCON1 0640 CRCEN

— CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRCISEL CRCGO LENDIAN — — — 0000

CRCCON2 0642

— — — DWIDTH4 DWIDTH3 DWIDTH2 DWIDTH1 DWIDTH0 — — — PLEN4 PLEN3 PLEN2 PLEN1 PLEN0 0000

CRCXORL 0644 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1

— 0000

CRCXORH 0646 X31 X30 X29 X28 X27 X26 X25 X24 X23 X22 X21 X20 X19 X18 X17 X16 0000

CRCDATL 0648 CRCDATL xxxx

CRCDATH 064A CRCDATH xxxx

CRCWDATL 064C CRCWDATL xxxx

CRCWDATH 064E CRCWDATH xxxx

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 4-22: CLOCK CONTROL REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

RCON 0740 TRAPR IOPUWR SBOREN RETEN

— DPSLP CM PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR (Note 1)

OSCCON 0742

— COSC2 COSC1 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK —LOCK — CF SOSCDRV SOSCEN OSWEN (Note 2)

CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0

— — — — — — — — 3140

OSCTUN 0748

— — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 0000

REFOCON 074E ROEN

— ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — 0000

HLVDCON 0756 HLVDEN

—HLSIDL— — — — — VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL 1 HLVDL0 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: RCON register Reset values are dependent on the type of Reset.

2: OSCCON register Reset values are dependent on the Configuration Fuses and by type of Reset.

TABLE 4-23: DEEP SLEEP REGISTER MAP

File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

All

Resets

DSCON 0758 DSEN

— — — — — — RTCCWDIS — — — — ULPWDIS DSBOR RELEASE 0000

DSWAKE 075A

— — — — — — — DSINT0 DSFLT — — DSWDT DSRTCC DSMCLR — DSPOR 0000

DSGPR0

(1)

075C DSGPR0 0000

DSGPR1

(1)

075E DSGPR1 0000

Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1: The Deep Sleep registers, DSGPR0 and DSGPR1, are only reset on a V

DD POR event.