Datasheet

 2011-2013 Microchip Technology Inc. DS39995D-page 355
PIC24FV32KA304 FAMILY
M
Microchip Internet Web Site ............................................. 358
MPLAB ASM30 Assembler, Linker, Librarian .................. 252
MPLAB Integrated Development
Environment Software .............................................. 251
MPLAB PM3 Device Programmer ................................... 254
MPLAB REAL ICE In-Circuit Emulator System ................ 253
MPLINK Object Linker/MPLIB Object Librarian ............... 252
N
Near Data Space ............................................................... 38
O
On-Chip Voltage Regulator .............................................. 248
Oscillator Configuration
Clock Switching ........................................................ 121
Enabling ........................................................... 121
Sequence ......................................................... 121
Configuration Bit Values for Clock Selection ........... 116
CPU Clocking Scheme ............................................ 116
Initial Configuration on POR .................................... 116
Reference Clock Output ........................................... 122
Output Compare
Cascaded (32-Bit) Mode .......................................... 151
Operations ............................................................... 153
Subcycle Resolution ................................................ 156
Synchronous, Trigger Modes ................................... 151
P
Packaging
Details ...................................................................... 328
Marking .................................................................... 325
PIC24F32KA304 Family Device Features (Summary) ....... 14
PIC24FV32KA304 Family Device
Features (Summary) .................................................. 13
Pinout Descriptions ............................................................ 16
Power-Saving ................................................................... 134
Power-Saving Features ................................................... 125
Clock Frequency, Clock Switching ........................... 125
Coincident Interrupts ................................................ 126
Instruction-Based Modes ......................................... 125
Deep Sleep ...................................................... 126
Idle ................................................................... 126
Sleep ................................................................ 125
Selective Peripheral Control .................................... 134
Ultra Low-Power Wake-up ....................................... 131
Voltage, Regulator-Based ........................................ 133
Deep Sleep Mode ............................................ 133
Retention Sleep Mode ..................................... 133
Run Mode ........................................................ 133
Sleep (Standby) Mode ..................................... 133
Product Identification System .......................................... 360
Program and Data Memory
Access Using Table Instructions ................................ 53
Addressing Space ...................................................... 51
Interfacing Spaces ..................................................... 51
Program Space Visibility ............................................ 55
Program Memory
Address Space ........................................................... 35
Data EEPROM ........................................................... 36
Device Configuration Words ...................................... 36
Hard Memory Vectors ................................................ 36
Memory Map .............................................................. 35
Organization ............................................................... 36
Program Verification ........................................................ 250
Pulse-Width Modulation (PWM) Mode ............................. 154
Pulse-Width Modulation.
See PWM.
PWM
Duty Cycle and Period ............................................. 155
R
Reader Response ............................................................ 359
Register Maps
A/D Converter ............................................................ 47
Analog Select ............................................................ 48
Clock Control ............................................................. 49
CPU Core .................................................................. 39
CRC ........................................................................... 49
CTMU ........................................................................ 48
Deep Sleep ................................................................ 49
I2Cx ........................................................................... 44
ICN ............................................................................ 40
Input Capture ............................................................. 42
Interrupt Controller ..................................................... 41
NVM ........................................................................... 50
Output Compare ........................................................ 43
Pad Configuration ...................................................... 46
PMD ........................................................................... 50
PORTA ...................................................................... 45
PORTB ...................................................................... 45
PORTC ...................................................................... 46
Real-Time Clock and Calendar (RTCC) .................... 48
SPIx ........................................................................... 45
Timer ......................................................................... 42
Triple Comparator ...................................................... 48
UARTx ....................................................................... 44
Ultra Low-Power Wake-up ......................................... 50
Registers
AD1CHITH (A/D Scan Compare Hit, High Word) .... 216
AD1CHITH (A/D Scan Compare Hit, Low Word) ..... 216
AD1CHS (A/D Sample Select) ................................ 215
AD1CON1 (A/D Control 1) ....................................... 211
AD1CON2 (A/D Control 2) ....................................... 212
AD1CON3 (A/D Control 3) ....................................... 213
AD1CON5 (A/D Control 5) ....................................... 214
AD1CSSH (A/D Input Scan Select, High Word) ...... 217
AD1CSSL (A/D Input Scan Select, Low Word) ....... 217
AD1CTMUENH (CTMU Enable, High Word) ........... 218
AD1CTMUENL (CTMU Enable, Low Word) ............ 218
ALCFGRPT (Alarm Configuration) .......................... 190
ALMINSEC (Alarm Minutes and Seconds Value) .... 194
ALMTHDY (Alarm Month and Day Value) ............... 193
ALWDHR (Alarm Weekday and Hours Value) ........ 193
ANSA (Analog Selection, PORTA) .......................... 136
ANSB (Analog Selection, PORTB) .......................... 137
ANSC (Analog Selection, PORTC) .......................... 137
CLKDIV (Clock Divider) ........................................... 119
CMSTAT (Comparator x Status) ............................. 228
CMxCON (Comparator x Control) ........................... 227
CORCON (CPU Control) ........................................... 33
CORCON (CPU Core Control) .................................. 80
CRCCON1 (CRC Control 1) .................................... 202
CRCCON2 (CRC Control 2) .................................... 203
CRCXORH (CRC XOR Polynomial, High Byte) ...... 204
CRCXORL (CRC XOR Polynomial, Low Byte) ........ 204
CTMUCON (CTMU Control 1) ................................. 234
CTMUCON2 (CTMU Control 2) ............................... 235
CTMUICON (CTMU Current Control) ...................... 237
CVRCON (Comparator Voltage
Reference Control) .......................................... 230