Datasheet

PIC24FV32KA304 FAMILY
DS39995D-page 35  2011-2013 Microchip Technology Inc.
4.0 MEMORY ORGANIZATION
As Harvard architecture devices, the PIC24F
microcontrollers feature separate program and data
memory space and bussing. This architecture also
allows the direct access of program memory from the
data space during code execution.
4.1 Program Address Space
The program address memory space of the
PIC24FV32KA304 family is 4M instructions. The space
is addressable by a 24-bit value derived from either the
23-bit Program Counter (PC) during program execution,
or from a table operation or data space remapping, as
described in Section 4.3 “Interfacing Program and
Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations, which use TBLPAG<7> to permit access to
the Configuration bits and Device ID sections of the
configuration memory space.
Memory maps for the PIC24FV32KA304 family of
devices are shown in Figure 4-1.
FIGURE 4-1: PROGRAM SPACE MEMORY MAP FOR PIC24FV32KA304 FAMILY DEVICES
000000h
0000FEh
000002h
000100h
F80010h
F80012h
FEFFFEh
FFFFFFh
000004h
000200h
0001FEh
000104h
Configuration Memory Space
User Memory Space
Note: Memory areas are not displayed to scale.
Reset Address
Device Config Registers
DEVID (2)
GOTO Instruction
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24FV32KA304
FF0000h
F7FFFEh
F80000h
800000h
7FFFFFh
Reserved
Unimplemented
Read ‘0’
Reset Address
DEVID (2)
GOTO Instruction
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
PIC24FV16KA304
Device Config Registers
Reserved
Unimplemented
Read ‘0’
002BFEh
User Flash
Program Memory
(11264 instructions)
7FFE00h
Data EEPROM
Data EEPROM
Flash
Program Memory
(5632 instructions)
0057FEh