Datasheet

 2011-2013 Microchip Technology Inc. DS39995D-page 281
PIC24FV32KA304 FAMILY
FIGURE 29-7: BROWN-OUT RESET CHARACTERISTICS
TABLE 29-26: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 1.8V to 3.6V PIC24F32KA3XX
2.0V to 5.5V PIC24FV32KA3XX
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  T
A  +125°C for Extended
Param
No.
Symbol Characteristic Min. Typ
(1)
Max. Units Conditions
SY10 TmcL MCLR
Pulse Width (low) 2 — — s
SY11 TPWRT Power-up Timer Period 50 64 90 ms
SY12 T
POR Power-on Reset Delay 1 5 10 s
SY13 TIOZ I/O High-Impedance from
MCLR
Low or Watchdog
Timer Reset
— — 100 ns
SY20 T
WDT Watchdog Timer Time-out
Period
0.85 1.0 1.15 ms 1.32 prescaler
3.4 4.0 4.6 ms 1:128 prescaler
SY25 T
BOR Brown-out Reset Pulse
Width
1— — s
SY35 T
FSCM Fail-Safe Clock Monitor
Delay
—2.0 2.3 s
SY45 T
RST Internal State Reset Time — 5 — s
SY50 T
VREG On-Chip Voltage Regulator
Output Delay
—10 — s (Note 2)
SY55 T
LOCK PLL Start-up Time — 100 — s
SY65 T
OST Oscillator Start-up Time — 1024 — TOSC
SY70 TDSWU Wake-up from Deep Sleep
Time
—100 — s Based on full discharge of
10 F capacitor on V
CAP;
includes T
POR and TRST
SY71 TPM Program Memory Wake-up
Time
—1 — s Sleep wake-up with
PMSLP = 0
SY72 T
LVR Retention Regulator
Wake-up Time
—250 — s
SY73 T
HVLD HVLD Interrupt Response
Time
—2 — s
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated.
2: This applies to PIC24FV32KA3XX devices only.
DC19
Reset (Due to BOR)
V
DDCORE
(Device in Brown-out Reset)
(Device not in Brown-out Reset)
TVREG + TRST
DC15
SY25