Datasheet

 2011-2013 Microchip Technology Inc. DS39995D-page 249
PIC24FV32KA304 FAMILY
If the WDT is enabled in hardware (FWDTEN<1:0> = 11),
it will continue to run during Sleep or Idle modes. When
the WDT time-out occurs, the device will wake and code
execution will continue from where the PWRSAV
instruction was executed. The corresponding SLEEP or
IDLE bit (RCON<3:2>) will need to be cleared in software
after the device wakes up.
The WDT Flag bit, WDTO (RCON<4>), is not auto-
matically cleared following a WDT time-out. To detect
subsequent WDT events, the flag must be cleared in
software.
26.3.1 WINDOWED OPERATION
The Watchdog Timer has an optional Fixed Window
mode of operation. In this Windowed mode, CLRWDT
instructions can only reset the WDT during the last 1/4
of the programmed WDT period. A CLRWDT instruction
executed before that window causes a WDT Reset,
similar to a WDT time-out.
Windowed WDT mode is enabled by programming the
Configuration bit, WINDIS (FWDT<6>), to ‘0’.
26.3.2 CONTROL REGISTER
The WDT is enabled or disabled by the FWDTEN<1:0>
Configuration bits. When both the FWDTEN<1:0>
Configuration bits are set, the WDT is always enabled.
The WDT can be optionally controlled in software when
the FWDTEN<1:0> Configuration bits have been pro-
grammed to ‘10’. The WDT is enabled in software by
setting the SWDTEN control bit (RCON<5>). The
SWDTEN control bit is cleared on any device Reset.
The software WDT option allows the user to enable the
WDT for critical code segments, and disable the WDT
during non-critical segments, for maximum power
savings. When the FWTEN<1:0> bits are set to ‘01’,
the WDT is only enabled in Run and Idle modes, and is
disabled in Sleep. Software control of the SWDTEN bit
(RCON<5>) is disabled with this setting.
FIGURE 26-2: WDT BLOCK DIAGRAM
Note: The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
LPRC Input
WDT Overflow
Wake from Sleep
31 kHz
Prescaler
Postscaler
FWPSA
SWDTEN
FWDTEN<1:0>
Reset
All Device Resets
Sleep or Idle Mode
LPRC Control
CLRWDT Instr.
PWRSAV Instr.
(5-Bit/7-Bit)
1:1 to 1:32.768
WDTPS<3:0>
1 ms/4 ms
Exit Sleep or
Idle Mode
WDT
Counter
Transition to
New Clock Source