Datasheet

PIC24FV32KA304 FAMILY
DS39995D-page 248  2011-2013 Microchip Technology Inc.
26.2 On-Chip Voltage Regulator
All of the PIC24FV32KA304 family devices power their
core digital logic at a nominal 3.0V. This may create an
issue for designs that are required to operate at a
higher typical voltage, as high as 5.0V. To simplify sys-
tem design, all devices in the “FV” family incorporate an
on-chip regulator that allows the device to run its core
logic from V
DD.
The regulator is always enabled and provides power to
the core from the other V
DD pins. A low-ESR capacitor
(such as ceramic) must be connected to the V
CAP pin
(Figure 26-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capaci-
tor is discussed in Section 2.4 “Voltage Regulator Pin
(VCAP)”, and in Section 29.1 “DC Characteristics”.
For “F” devices, the regulator is disabled. Instead, core
logic is powered directly from V
DD. This allows the
devices to operate at an overall lower allowable voltage
range (1.8V-3.6V).
26.2.1 VOLTAGE REGULATOR TRACKING
MODE AND LOW-VOLTAGE
DETECTION
For all PIC24FV32KA304 devices, the on-chip regula-
tor provides a constant voltage of 3.2V nominal to the
digital core logic. The regulator can provide this level
from a V
DD of about 3.2V, all the way up to the device’s
V
DDMAX. It does not have the capability to boost VDD
levels below 3.2V. In order to prevent “brown-out” con-
ditions when the voltage drops too low for the regulator,
the regulator enters Tracking mode. In Tracking mode,
the regulator output follows V
DD with a typical voltage
drop of 150 mV.
When the device enters Tracking mode, it is no longer
possible to operate at full speed. To provide information
about when the device enters Tracking mode, the
on-chip regulator includes a simple, High/Low-Voltage
Detect (HLVD) circuit. When V
DD drops below full-speed
operating voltage, the circuit sets the High/Low-Voltage
Detect Interrupt Flag, HLVDIF (IFS4<8>). This can be
used to generate an interrupt and put the application into
a low-power operational mode or trigger an orderly
shutdown. Maximum device speeds as a function of V
DD
are shown in Section 29.1 “DC Characteristics”, in
Figure 29-1 and Figure 29-1.
26.2.2 ON-CHIP REGULATOR AND POR
For PIC24FV32KA304 devices, it takes a brief time,
designated as T
PM, for the Voltage Regulator to gener-
ate a stable output. During this time, code execution is
disabled. T
PM (DC Specification SY71) is applied every
time the device resumes operation after any
power-down, including Sleep mode.
FIGURE 26-1: CONNECTIONS FOR THE
ON-CHIP REGULATOR
26.3 Watchdog Timer (WDT)
For the PIC24FV32KA304 family of devices, the WDT
is driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
The nominal WDT clock source from LPRC is 31 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the FWPSA Configuration bit.
With a 31 kHz input, the prescaler yields a nominal
WDT time-out period (T
WDT) of 1 ms in 5-bit mode or
4 ms in 7-bit mode.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the Configuration bits,
WDTPS<3:0> (FWDT<3:0>), which allow the selection
of a total of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranging
from 1 ms to 131 seconds, can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAV instruction is executed
(i.e., Sleep or Idle mode is entered)
• When the device exits Sleep or Idle mode to
resume normal operation
•By a CLRWDT instruction during normal execution
VDD
VCAP
VSS
PIC24FV32KA304
CEFC
5.0V
(10 F typ)
Regulator Enabled
(1)
:
Note 1: These are typical operating voltages. Refer to
Section 29.0 “Electrical Characteristics”
for the full operating ranges of V
DD.