Datasheet

PIC24FV32KA304 FAMILY
DS39995D-page 214  2011-2013 Microchip Technology Inc.
REGISTER 22-4: AD1CON5: A/D CONTROL REGISTER 5
R/W-0 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 R/W-0
ASEN
(1)
LPEN CTMREQ BGREQ r — ASINT1 ASINT0
bit 15 bit 8
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
— — — — WM1 WM0 CM1 CM0
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 ASEN: Auto-Scan Enable bit
(1)
1 = Auto-scan is enabled
0 = Auto-scan is disabled
bit 14 LPEN: Low-Power Enable bit
1 = Returns to Low-Power mode after scan
0 = Remains in Full-Power mode after scan
bit 13 CTMREQ: CTMU Request bit
1 = CTMU is enabled when the A/D is enabled and active
0 = CTMU is not enabled by the A/D
bit 12 BGREQ: Band Gap Request bit
1 = Band gap is enabled when the A/D is enabled and active
0 = Band gap is not enabled by the A/D
bit 11 Reserved: Maintain as ‘0’
bit 10 Unimplemented: Read as ‘0’
bit 9-8 ASINT<1:0>: Auto-Scan (Threshold Detect) Interrupt Mode bits
11 = Interrupt after a Threshold Detect sequence completed and a valid compare has occurred
10 = Interrupt after a valid compare has occurred
01 = Interrupt after a Threshold Detect sequence completed
00 = No interrupt
bit 7-4 Unimplemented: Read as ‘0’
bit 3-2 WM<1:0>: Write Mode bits
11 = Reserved
10 = Auto-compare only (conversion results are not saved, but interrupts are generated when a valid
match, as defined by the CMx and ASINTx bits, occurs)
01 = Convert and save (conversion results are saved to locations as determined by the register bits
when a match, as defined by the CMx bits, occurs)
00 = Legacy operation (conversion data is saved to a location determined by the buffer register bits)
bit 1-0 CM<1:0>: Compare Mode bits
11 = Outside Window mode (valid match occurs if the conversion result is outside of the window defined
by the corresponding buffer pair)
10 = Inside Window mode (valid match occurs if the conversion result is inside the window defined by the
corresponding buffer pair)
01 = Greater Than mode (valid match occurs if the result is greater than the value in the corresponding
buffer register)
00 = Less Than mode (valid match occurs if the result is less than the value in the corresponding buffer
register)
Note 1: When using auto-scan with Threshold Detect (ASEN = 1), do not configure the sample clock source to
Auto-Convert mode (SSRCx = 7). Any other available SSRCx selection is valid. To use auto-convert as
the sample clock source (SSRCx = 7), make sure ASEN is cleared.