Datasheet

 2011-2013 Microchip Technology Inc. DS39995D-page 167
PIC24FV32KA304 FAMILY
bit 1-0 PPRE<1:0>: Primary Prescale bits (Master mode)
11 = Primary prescale 1:1
10 = Primary prescale 4:1
01 = Primary prescale 16:1
00 = Primary prescale 64:1
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
Note 1: The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed
SPI modes (FRMEN = 1).
REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
FRMEN SPIFSD SPIFPOL
— — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — SPIFE SPIBEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 FRMEN: Framed SPIx Support bit
1 = Framed SPIx support is enabled
0 = Framed SPIx support is disabled
bit 14 SPIFSD: SPIx Frame Sync Pulse Direction Control on SSx
Pin bit
1 = Frame Sync pulse input (slave)
0 = Frame Sync pulse output (master)
bit 13 SPIFPOL: SPIx Frame Sync Pulse Polarity bit (Frame mode only)
1 = Frame Sync pulse is active-high
0 = Frame Sync pulse is active-low
bit 12-2 Unimplemented: Read as ‘0’
bit 1 SPIFE: SPIx Frame Sync Pulse Edge Select bit
1 = Frame Sync pulse coincides with the first bit clock
0 = Frame Sync pulse precedes the first bit clock
bit 0 SPIBEN: SPIx Enhanced Buffer Enable bit
1 = Enhanced buffer is enabled
0 = Enhanced buffer is disabled (Legacy mode)