Datasheet

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DS39995D-page 156  2011-2013 Microchip Technology Inc.
15.4 Subcycle Resolution
The DCBx bits (OCxCON2<10:9>) provide for resolu-
tion better than one instruction cycle. When used, they
delay the falling edge generated from a match event by
a portion of an instruction cycle.
For example, setting DCB<1:0> = 10 causes the falling
edge to occur halfway through the instruction cycle in
which the match event occurs, instead of at the
beginning. These bits cannot be used when
OCM<2:0> = 001. When operating the module in PWM
mode (OCM<2:0> = 110 or 111), the DCBx bits will be
double-buffered.
The DCBx bits are intended for use with a clock source
identical to the system clock. When an OCx module
with enabled prescaler is used, the falling edge delay
caused by the DCBx bits will be referenced to the
system clock period, rather than the OCx module’s
period.
TABLE 15-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)
(1)
TABLE 15-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (F
CY = 16 MHz)
(1)
PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz
Prescaler Ratio 8111111
Period Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh
Resolution (bits) 16 16 15 12 10 7 5
Note 1: Based on F
CY = FOSC/2; Doze mode and PLL are disabled.
PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz
Prescaler Ratio 8111111
Period Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh
Resolution (bits) 16 16 15 12 10 7 5
Note 1: Based on F
CY = FOSC/2; Doze mode and PLL are disabled.