Datasheet

PIC24FV32KA304 FAMILY
DS39995D-page 154  2011-2013 Microchip Technology Inc.
15.3 Pulse-Width Modulation (PWM)
Mode
In PWM mode, the output compare module can be
configured for edge-aligned or center-aligned pulse
waveform generation. All PWM operations are
double-buffered (buffer registers are internal to the
module and are not mapped into SFR space).
To configure the output compare module for
edge-aligned PWM operation:
1. Calculate the desired ON time and load it into
the OCxR register.
2. Calculate the desired period and load it into the
OCxRS register.
3. Select the current OCx as the synchronization
source by writing 0x1F to SYNCSEL<4:0>
(OCxCON2<4:0>) and ‘0’ to OCTRIG
(OCxCON2<7>).
4. Select a clock source by writing the
OCTSEL2<2:0> (OCxCON<12:10>) bits.
5. Enable interrupts, if required, for the timer and
output compare modules. The output compare
interrupt is required for PWM Fault pin utilization.
6. Select the desired PWM mode in the OCM<2:0>
(OCxCON1<2:0>) bits.
7. If a timer is selected as a clock source, set the
TMRy prescale value and enable the time base by
setting the TON (TxCON<15>) bit.
FIGURE 15-2: OUTPUT COMPARE x BLOCK DIAGRAM (DOUBLE-BUFFERED,
16-BIT PWM MODE)
OCxR and DCB<1:0> Buffers
Comparator
OCxTMR
OCxCON1
OCxCON2
OC Output Timing
OCx Interrupt
OCx Pin
OCxRS Buffer
Comparator
and Fault Logic
Match
Match
Trigger and
Sync Logic
Clock
Select
Increment
Reset
OC Clock
Sources
Trigger and
Sync Sources
Reset
Match Event
OCFA/OCFB/CxOUT
OCTSELx
SYNCSELx
TRIGSTAT
TRIGMODE
OCTRIG
OCMx
OCINV
OCTRIS
FLTOUT
FLTTRIEN
FLTMD
ENFLTx
OCFLTx
OCxR and DCB<1:0>
OCxRS
Event
Event
Rollover
Rollover/Reset
Rollover/Reset
DCB<1:0>