Datasheet

PIC24F16KA102 FAMILY
DS39927C-page 146  2008-2011 Microchip Technology Inc.
REGISTER 17-3: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
— — — — — — AMSK9 AMSK8
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-10 Unimplemented: Read as ‘0’
bit 9-0 AMSK<9:0>: Mask for Address Bit x Select bits
1 = Enable masking for bit x of incoming message address; bit match is not required in this position
0 = Disable masking for bit x; bit match is required in this position
REGISTER 17-4: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
— — — SMBUSDEL OC1TRIS
(2,3)
RTSECSEL1
(1,3)
RTSECSEL0
(1,3)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-5 Unimplemented: Read as ‘0’
bit 4 SMBUSDEL: SMBus SDA Input Delay Select bit
1 = The I
2
C module is configured for a longer SMBus input delay (nominal 300 ns delay)
0 = The 1
2
C module is configured for a legacy input delay (nominal 150 ns delay)
bit 0 Unimplemented: Read as ‘0’
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL<10>) bit needs to be set.
2: To enable the actual OC1 output, the OCPWM1 module has to be enabled.
3: Bits<3:1> are described in related chapters.