Datasheet

 2008-2011 Microchip Technology Inc. DS39927C-page 105

PIC24F16KA102 FAMILY

(1)

R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

DSEN — — — — — — —

bit 15 bit 8

U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/C-0, HS

— — — — — — DSBOR

(2)

RELEASE

bit 7 bit 0

Legend: C = Clearable bit HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 15 DSEN: Deep Sleep Enable bit

1 = Enters Deep Sleep on execution of PWRSAV #0

0 = Enters normal Sleep on execution of PWRSAV #0

bit 14-2 Unimplemented: Read as ‘0’

bit 1 DSBOR: Deep Sleep BOR Event bit

(2)

1 = The DSBOR was active and a BOR event was detected during Deep Sleep

0 = The DSBOR was not active, or was active but did not detect a BOR event during Deep Sleep

bit 0 RELEASE: I/O Pin State Release bit

1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry

0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and

LAT bits to control their states

Note 1: All register bits are reset only in the case of a POR event outside of Deep Sleep mode.

2: Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this

re-arms POR.