PIC24F16KA102 Family Data Sheet 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology 2008-2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC24F16KA102 FAMILY 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP Technology Power Management Modes: Analog Features: • • • • • 10-Bit, up to 9-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/ Output Configuration • Charge Time Measurement Unit (CTMU): - Used for capacitance sensing - Time measurement, down to 1 ns resolution - Delay/pulse generation, down to 1 ns r
PIC24F16KA102 FAMILY Pin Diagrams 20-Pin PDIP, SSOP, SOIC(2) 1 2 3 4 5 6 7 8 9 10 PIC24XXKAX01 MCLR/VPP/RA5 PGC2/AN0/VREF+/CN2/RA0 PGD2/AN1/VREF-/CN3/RA1 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/CN5/RB1 U1RX/CN6/RB2 OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2 OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3 PGD3/SOSCI/U2RTS/U2BCLK/CN1/RB4 PGC3/SOSCO/T1CK/U2CTS/CN0/RA4 VDD VSS REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/SCK1/CTED2/CN14/RB12
PIC24F16KA102 FAMILY Pin Diagrams (Continued) PGD2/AN1/VREF-/CN3/RA1 PGC2/AN0/VREF+/CN2/RA0 MCLR/VPP/RA5 VDD VSS 20-Pin QFN(1,2) 20 19 18 17 16 15 1 14 2 3 PIC24FXXKA10213 12 4 11 5 6 7 8 9 10 REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/ CN13/RB13 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 PGD3/SOSCI/U2RTS/CN1/U2BCLK/RB4 PGC3/SOSCO/T1CK/U2CTS/CN0/RA4 U1TX/INT0/CN23/RB7 U1CTS/SCL1/CN22/RB8 U1RTS/U1BCLK/SDA1/CN21/RB9 PGD1/AN2/C1IND/C
PIC24F16KA102 FAMILY Pin Diagrams (Continued) AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR/VPP/RA5 VDD Vss REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/OCFA/C1OUT/INT1/CN12/RB14 28-Pin QFN(2,3) 28 27 26 25 24 23 22 1 2 3 4 5 6 7 PIC24FXXKA102 8 9 10 11 12 13 14 21 20 19 18 17 16 15 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/CTED2/CN14/RB12 PGC2/SCK1/CN15/RB11 PGD2/SDI1/PMD2/CN16/RB10 OC1/C2OUT/INT2/CTED1/CN8/RA6 IC1/CN9/RA7 U1RTS/U1BCLK/SDA1/CN21/RB9 SOSCI/U2RTS/U2BCLK/CN1/RB4 SOSCO/T1CK/U2CTS/CN0/RA4 VDD PG
PIC24F16KA102 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 17 3.0 CPU .....................................................................................................
PIC24F16KA102 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced.
PIC24F16KA102 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • • • • PIC24F08KA101 PIC24F16KA101 PIC24F08KA102 PIC24F16KA102 The PIC24F16KA102 family introduces a new line of extreme low-power Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance.
PIC24F16KA102 FAMILY The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.3 1.1.4 1.
PIC24F16KA102 FAMILY Program Memory (bytes) 16K Program Memory (instructions) 2816 5632 2816 5632 512 Interrupt Sources (soft vectors/NMI traps) 30 (26/4) PORTA<6:0> PORTB<15:12, 9:7, 4, 2:0> PORTA<7:0> PORTB<15:0> 18 24 Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) 3 1 Input Capture Channels 1 Output Compare/PWM Channels 1 Input Change Notification Interrupt 16K 1536 Data EEPROM Memory (bytes) Total I/O Pins 8K DC – 32 MHz Data Memory (bytes) I/O Ports PIC24F
PIC24F16KA102 FAMILY FIGURE 1-1: PIC24F16KA102 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller 16 16 16 8 Data Latch PSV and Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTA(1) RA<0:7> 16 23 16 Read AGU Write AGU Address Latch Program Memory PORTB(1) Data EEPROM RB<0:15> Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 Inst Register Instruction Decode and Control Control Sign
PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS Pin Number 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN 28-Pin SPDIP/ SSOP/SOIC 28-Pin QFN I/O Input Buffer 2 19 2 27 I ANA AN1 3 20 3 28 I ANA AN2 4 1 4 1 I ANA AN3 5 2 5 2 I ANA AN4 7 4 6 3 I ANA Function AN0 AN5 8 5 7 4 I ANA AN10 17 14 25 22 I ANA AN11 16 13 24 21 I ANA AN12 15 12 23 20 I ANA U1BCLK 13 10 18 15 O — Description A/D Analog Inputs UART1 IrDA® Baud C
PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN 28-Pin SPDIP/ SSOP/SOIC 28-Pin QFN I/O Input Buffer CN0 10 7 12 9 I ST CN1 9 6 11 8 I ST CN2 2 19 2 27 I ST CN3 3 20 3 28 I ST CN4 4 1 4 1 I ST CN5 5 2 5 2 I ST ST Function CN6 6 3 6 3 I CN7 — — 7 4 I ST CN8 14 11 20 17 I ST CN9 — — 19 16 I ST CN11 18 15 26 23 I ST CN12 17 14 25 22 I ST CN
PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN 28-Pin SPDIP/ SSOP/SOIC 28-Pin QFN I/O Input Buffer PGC1 5 2 5 2 I/O ST In-Circuit Debugger and ICSP™ Programming Clock PGD1 4 1 4 1 I/O ST In-Circuit Debugger and ICSP Programming Data PGC2 2 19 22 19 I/O ST In-Circuit Debugger and ICSP Programming Clock PGD2 3 20 21 18 I/O ST In-Circuit Debugger and ICSP Programming Data PGC3 10 7 15
PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 20-Pin PDIP/SSOP/ SOIC 20-Pin QFN 28-Pin SPDIP/ SSOP/SOIC 28-Pin QFN I/O Input Buffer Description T1CK 10 7 12 9 I ST Timer1 Clock T2CK 18 15 26 23 I ST Timer2 Clock T3CK 18 15 26 23 I ST Timer3 Clock U1CTS 12 9 17 14 I ST UART1 Clear to Send Input U1RTS 13 10 18 15 O — UART1 Request to Send Output U1RX 6 3 6 3 I ST UART1 Receive U1TX 11 8 16
PIC24F16KA102 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • VCAP pins (see Section 2.
PIC24F16KA102 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended.
PIC24F16KA102 FAMILY Voltage Regulator Pin (VCAP) Note: This section applies only to PIC24F K devices with an on-chip voltage regulator. Refer to Section 29.0 “Electrical Characteristics” for information on VDD and VDDCORE. FIGURE 2-3: Some of the PIC24F K devices have an internal voltage regulator. These devices have the voltage regulator output brought out on the VCAP pin.
PIC24F16KA102 FAMILY CONSIDERATIONS FOR CERAMIC CAPACITORS In recent years, large value, low-voltage, surface-mount ceramic capacitors have become very cost effective in sizes up to a few tens of microfarad. The low-ESR, small physical size and other properties make ceramic capacitors very attractive in many types of applications. Ceramic capacitors are suitable for use with the internal voltage regulator of this microcontroller.
PIC24F16KA102 FAMILY 2.6 External Oscillator Pins FIGURE 2-5: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins.
PIC24F16KA102 FAMILY NOTES: DS39927C-page 22 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY 3.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the CPU, refer to the “PIC24F Family Reference Manual”, Section 2. “CPU” (DS39703). The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field.
PIC24F16KA102 FAMILY FIGURE 3-1: PIC24F CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic 23 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory Data EEPROM EA MUX Address Bus Data Latch ROM Latch 24 16 Instruction Decode and Control Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support Literal Data 16 1
PIC24F16KA102 FAMILY FIGURE 3-2: PROGRAMMER’S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL — — — — — — — DC IPL RA N OV Z C 2 1 0 15 15 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Regis
PIC24F16KA102 FAMILY 3.
PIC24F16KA102 FAMILY REGISTER 3-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0 — — — — IPL3(1) PSV — — bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priority Level Status bit(1)
PIC24F16KA102 FAMILY 3.3.2 DIVIDER 3.3.3 The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1.
PIC24F16KA102 FAMILY 4.0 MEMORY ORGANIZATION As with Harvard architecture devices, the PIC24F microcontrollers feature separate program and data memory space and busing. This architecture also allows the direct access of program memory from the data space during code execution. 4.1 Program Address Space The user access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh).
PIC24F16KA102 FAMILY 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.3 In the PIC24F16KA102 family, the data EEPROM is mapped to the top of the user program memory space, starting at address, 7FFE00, and expanding up to address, 7FFFFF. The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented.
PIC24F16KA102 FAMILY 4.2 4.2.1 Data Address Space DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all the data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range.
PIC24F16KA102 FAMILY 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all EA calculations are internally scaled to step through word-aligned memory.
2008-2011 Microchip Technology Inc.
ICN REGISTER MAP File Addr Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 CNEN1 0060 CN15IE(1) CN14IE CN13IE CN12IE CN11IE(1) — CN9IE CN8IE CN7IE(1) — CN27IE(1) — — CN24IE(1) CN23IE CNPU1 0068 CN15PUE(1) CN14PUE CN13PUE CN12PUE CN11PUE(1) — CN9PUE CN8PUE CN27PUE(1) — — CNEN2 0062 — CN30IE CNPU2 006A — CNPD1 0070 CN15PDE(1) CNPD2 0072 — Legend: Note 1: CN30PUE CN29PUE — CN14PDE CN13PDE CN12PDE CN11PDE(1) — CN9PDE CN30PDE CN29PDE CN27PDE(1)
2008-2011 Microchip Technology Inc.
File Name Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 I2C1RCV 0200 — — — — — — — — I2C1 Receive Register 0000 I2C1TRN 0202 — — — — — — — — I2C1 Transmit Register 00FF I2C1BRG 0204 — — — — — — — I2C1CON 0206 I2CEN — A10M DISSLW SMEN GCEN STREN I2C1STAT 0208 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV I2C1ADD 020A — — — — — — I2C1MSK 020C — — — — — — Legend: Addr Bit 3 Bit 2 Bit 1 Bit 0 I2C1 Baud Rate Generato
2008-2011 Microchip Technology Inc.
A/D REGISTER MAP File Name Addr ADC1BUF0 0300 A/D Data Buffer 0 xxxx ADC1BUF1 0302 A/D Data Buffer 1 xxxx ADC1BUF2 0304 A/D Data Buffer 2 xxxx ADC1BUF3 0306 A/D Data Buffer 3 xxxx ADC1BUF4 0308 A/D Data Buffer 4 xxxx ADC1BUF5 030A A/D Data Buffer 5 xxxx ADC1BUF6 030C A/D Data Buffer 6 xxxx ADC1BUF7 030E A/D Data Buffer 7 xxxx ADC1BUF8 0310 A/D Data Buffer 8 xxxx ADC1BUF9 0312 A/D Data Buffer 9 xxxx ADC1BUFA 0314 A/D Data Buffer 10 xxxx ADC1BUFB 0316 A/D Data
2008-2011 Microchip Technology Inc.
File Name CLOCK CONTROL REGISTER MAP Addr Bit 15 Bit 14 Bit 13 RCON 0740 TRAPR OSCCON 0742 — COSC2 COSC1 Bit 12 Bit 11 — — DPSLP — COSC0 — NOSC2 NOSC1 IOPUWR SBOREN Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 PMSLP EXTR SWR SWDTEN WDTO SLEEP IDLE NOSC0 CLKLOCK — LOCK — CF — Bit 1 Bit 0 All Resets BOR POR (Note 1) SOSCEN OSWEN (Note 2) CLKDIV 0744 ROI DOZE2 DOZE1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — — — — — — — — OSCTUN 0748
PIC24F16KA102 FAMILY 4.2.5 SOFTWARE STACK 4.3 In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as depicted in Figure 4-4. For a PC push during any CALL instruction, the MSB of the PC is Zero-Extended before the push, ensuring that the MSB is always clear.
PIC24F16KA102 FAMILY TABLE 4-24: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space Access Type Program Space Address <23> <22:16> <15> <14:1> <0> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 2: 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 User 0 PSVPAG<7:0>(2) Data EA<14:0
PIC24F16KA102 FAMILY 4.3.2 DATA ACCESS FROM PROGRAM MEMORY AND DATA EEPROM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program memory without going through data space. It also offers a direct method of reading or writing a word of any address within data EEPROM memory. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data.
PIC24F16KA102 FAMILY 4.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into an 8K word page (in PIC24F08KA1XX devices) and a 16K word page (in PIC24F16KA1XX devices) of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H).
PIC24F16KA102 FAMILY 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Flash Programming, refer to the “PIC24F Family Reference Manual”, Section 4. “Program Memory” (DS39715). The PIC24FJ64GA family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable when operating with VDD over 1.8V.
PIC24F16KA102 FAMILY 5.2 RTSP Operation The PIC24F Flash program memory array is organized into rows of 32 instructions or 96 bytes. RTSP allows the user to erase blocks of 1 row, 2 rows and 4 rows (32, 64 and 128 instructions) at a time and to program one row at a time. It is also possible to program single words. The 1-row (96 bytes), 2-row (192 bytes) and 4-row (384 bytes) erase blocks, and single row write block (96 bytes) are edge-aligned, from the beginning of program memory.
PIC24F16KA102 FAMILY REGISTER 5-1: R/SO-0, HC WR NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0 WREN R/W-0 R/W-0 WRERR (4) PGMONLY U-0 U-0 U-0 U-0 — — — — bit 15 U-0 — bit 8 R/W-0 ERASE R/W-0 NVMOP5 R/W-0 (1) R/W-0 (1) R/W-0 (1) NVMOP4 NVMOP3 NVMOP2 R/W-0 (1) NVMOP1 R/W-0 (1) NVMOP0(1) bit 7 bit 0 SO = Settable Only bit Legend: HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set R = Readable bit ‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, read
PIC24F16KA102 FAMILY 5.5.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time by erasing the programmable row. The general process is: 1. 2. 3. Read a row of program memory (32 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase a row (see Example 5-1): a) Set the NVMOP bits (NVMCON<5:0>) to ‘011000’ to configure for row erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits.
PIC24F16KA102 FAMILY EXAMPLE 5-3: LOADING THE WRITE BUFFERS – ASSEMBLY LANGUAGE CODE ; Set up NVMCON for row programming operations MOV #0x4004, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x1500, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0,
PIC24F16KA102 FAMILY EXAMPLE 5-5: INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE DISI #5 ; Block all interrupts for next 5 instructions MOV MOV MOV MOV BSET NOP NOP BTSC BRA #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR NVMCON, #15 $-2 EXAMPLE 5-6: ; ; ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence 2 NOPs required after setting WR Wait for the sequence to be completed INITIATING A PROGRAMMING SEQUENCE – ‘C’ LANGUAGE CODE // C example using MPLAB C30 as
PIC24F16KA102 FAMILY 6.0 Note: DATA EEPROM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Data EEPROM, refer to the “PIC24F Family Reference Manual”, Section 5. “Data EEPROM” (DS39720). The data EEPROM memory is a Nonvolatile Memory (NVM), separate from the program and volatile data RAM.
PIC24F16KA102 FAMILY REGISTER 6-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER R/S-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 WR WREN WRERR PGMONLY — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — ERASE NVMOP5 NVMOP4 NVMOP3 NVMOP2 NVMOP1 NVMOP0 bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ R = Readable bit W = Writable bit S = Settable bit HC = Hardware Clearable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is un
PIC24F16KA102 FAMILY 6.3 NVM Address Register As with Flash program memory, the NVM Address Registers, NVMADRU and NVMADR, form the 24-bit Effective Address (EA) of the selected row or word for data EEPROM operations. The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA.
PIC24F16KA102 FAMILY 6.4.1 ERASE DATA EEPROM A typical erase sequence is provided in Example 6-2. This example shows how to do a one-word erase. Similarly, a four-word erase and an eight-word erase can be done. This example uses ‘C’ library procedures to manage the Table Pointer (builtin_tblpage and builtin_tbloffset) and the Erase Page Pointer (builtin_tblwtl). The memory unlock sequence (builtin_write_NVM) also sets the WR bit to initiate the operation and returns control when complete.
PIC24F16KA102 FAMILY 6.4.1.1 Data EEPROM Bulk Erase 6.4.2 SINGLE-WORD WRITE To erase the entire data EEPROM (bulk erase), the address registers do not need to be configured because this operation affects the entire data EEPROM. The following sequence helps in performing bulk erase: To write a single word in the data EEPROM, the following sequence must be followed: 1. 2. 2. 3. 4. 5. Configure NVMCON to Bulk Erase mode. Clear NVMIF status bit and enable NVM interrupt (optional).
PIC24F16KA102 FAMILY 6.4.3 READING THE DATA EEPROM To read a word from data EEPROM, the table read instruction is used. Since the EEPROM array is only 16 bits wide, only the TBLRDL instruction is needed. The read operation is performed by loading TBLPAG and WREG with the address of the EEPROM location, followed by a TBLRDL instruction.
PIC24F16KA102 FAMILY 7.0 RESETS Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Resets, refer to the “PIC24F Family Reference Manual”, Section 40. “Reset with Programmable Brown-out Reset” (DS39728). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST.
PIC24F16KA102 FAMILY RCON: RESET CONTROL REGISTER(1) REGISTER 7-1: R/W-0, HS R/W-0, HS R/W-0 U-0 U-0 R/C-0, HS R/W-0, HS R/W-0 TRAPR IOPUWR SBOREN — — DPSLP CM PMSLP bit 15 bit 8 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS EXTR SWR SWDTEN(2) WDTO SLEEP IDLE BOR POR bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is s
PIC24F16KA102 FAMILY RCON: RESET CONTROL REGISTER(1) (CONTINUED) REGISTER 7-1: bit 3 SLEEP: Wake-up from Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up from Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred (the BOR is also set after a POR) 0 = A Brown-out Reset has not occurred bit 0 POR: Power-on Reset Flag bit 1 = A Power-up Reset has
PIC24F16KA102 FAMILY 7.1 Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen, as shown in Table 7-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 9.0 “Oscillator Configuration” for further details. TABLE 7-2: OSCILLATOR SELECTION vs.
PIC24F16KA102 FAMILY 7.2.1 POR AND LONG OSCILLATOR START-UP TIMES The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate.
PIC24F16KA102 FAMILY 7.5.2 DETECTING BOR When BOR is enabled, the BOR bit (RCON<1>) is always reset to ‘1’ on any BOR or POR event. This makes it difficult to determine if a BOR event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR and BOR bits are reset to ‘0’ in the software immediately after any POR event.
PIC24F16KA102 FAMILY 8.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Interrupt Controller, refer to the “PIC24F Family Reference Manual”, Section 8. “Interrupts” (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the CPU.
PIC24F16KA102 FAMILY Decreasing Natural Order Priority FIGURE 8-1: Note 1: DS39927C-page 64 PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Ve
PIC24F16KA102 FAMILY TABLE 8-1: TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error Reserved 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 000112h Reserved TABLE 8-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Source ADC1 Conversion Done Vector Number IVT Address 13 00002Eh Interrupt Bi
PIC24F16KA102 FAMILY 8.3 Interrupt Control and Status Registers The PIC24F16KA102 family of devices implements a total of 22 registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0, IFS1, IFS3 and IFS4 IEC0, IEC1, IEC3 and IEC4 IPC0 through IPC5, IPC7 and IPC15 through IPC19 • INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources.
PIC24F16KA102 FAMILY REGISTER 8-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC — — — — — — — DC(1) bit 15 bit 8 R/W-0, HSC IPL2 R/W-0, HSC R/W-0, HSC R-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC R/W-0, HSC IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) (2,3) bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-9
PIC24F16KA102 FAMILY REGISTER 8-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0, HSC R/W-0 U-0 U-0 — — — — IPL3(2) PSV(1) — — bit 7 bit 0 Legend: C = Clearable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-4 Unimplemented: Read as ‘0’ bit 3 IPL3: CPU Interrupt Priori
PIC24F16KA102 FAMILY REGISTER 8-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — MATHERR ADDRERR STKERR OSCFAIL — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrup
PIC24F16KA102 FAMILY REGISTER 8-4: INTCON2: INTERRUPT CONTROL REGISTER2 R/W-0 R-0, HSC U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — INT2EP INT1EP INT0EP bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Us
PIC24F16KA102 FAMILY REGISTER 8-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 R/W-0, HS NVMIF bit 15 U-0 — R/W-0, HS AD1IF R/W-0, HS U1TXIF R/W-0, HS U1RXIF R/W-0, HS SPI1IF R/W-0, HS SPF1IF R/W-0, HS T3IF bit 8 R/W-0, HS T2IF bit 7 U-0 — U-0 — U-0 — R/W-0, HS T1IF R/W-0, HS OC1IF R/W-0, HS IC1IF R/W-0, HS INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-4 bit 3 bit 2 bit 1 bit 0 HS = Hardware Settable bit W =
PIC24F16KA102 FAMILY REGISTER 8-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0, HS U2TXIF bit 15 R/W-0, HS U2RXIF U-0 — U-0 — R/W-0, HS INT2IF U-0 — U-0 — Legend: R = Readable bit -n = Value at POR bit 14 bit 13 bit 12-5 bit 4 bit 3 bit 2 bit 1 bit 0 U-0 — U-0 — bit 8 U-0 — R/W-0, HS INT1IF R/W-0, HS CNIF bit 7 bit 15 U-0 — R/W-0, HS CMIF R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0 HS = Hardware Settable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is
PIC24F16KA102 FAMILY REGISTER 8-7: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0, HS U-0 U-0 U-0 U-0 U-0 U-0 — RTCIF — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIF: Real-Time Clock and Calendar Interrupt Flag Status
PIC24F16KA102 FAMILY REGISTER 8-8: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0, HS U-0 U-0 U-0 U-0 R/W-0, HS — — CTMUIF — — — — HLVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 — — — — CRCIF U2ERIF U1ERIF — bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIF: CT
PIC24F16KA102 FAMILY REGISTER 8-9: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 R/W-0 NVMIE bit 15 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 T2IE bit 7 U-0 — U-0 — U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-4 bit 3 bit 2 bit 1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ =
PIC24F16KA102 FAMILY REGISTER 8-10: R/W-0 U2TXIE bit 15 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2RXIE R/W-0 INT2IE U-0 — U-0 — U-0 — U-0 — R/W-0 INT1IE R/W-0 CNIE bit 7 Legend: R = Readable bit -n = Value at POR bit 14 bit 13 bit 12-5 bit 4 bit 3 bit 2 bit 1 bit 0 U-0 — U-0 — bit 8 U-0 — bit 15 U-0 — W = Writable bit ‘1’ = Bit is set R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U2TXIE: UART2 Trans
PIC24F16KA102 FAMILY REGISTER 8-11: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 — RTCIE — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrupt request is enab
PIC24F16KA102 FAMILY REGISTER 8-12: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 — — CTMUIE — — — — HLVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 — — — — CRCIE U2ERIE U1ERIE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-14 Unimplemented: Read as ‘0’ bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request
PIC24F16KA102 FAMILY REGISTER 8-13: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — T1IP2 T1IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — IC1IP2 IC1IP1 IC1IP0 — INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T1I
PIC24F16KA102 FAMILY REGISTER 8-14: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — T2IP2 T2IP1 T2IP0 — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 T2IP<2:0>: Timer2 Interrupt Priority bits 111 = Interrupt is Priority
PIC24F16KA102 FAMILY REGISTER 8-15: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U1RXIP2 U1RXIP1 U1RXIP0 — SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — SPF1IP2 SPF1IP1 SPF1IP0 — T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-1
PIC24F16KA102 FAMILY REGISTER 8-16: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — NVMIP2 NVMIP1 NVMIP0 — — — — bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — AD1IP2 AD1IP1 AD1IP0 — U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 NVMIP<2:0>: NVM Inter
PIC24F16KA102 FAMILY REGISTER 8-17: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CNIP2 CNIP1 CNIP0 — CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — MI2C1P2 MI2C1P1 MI2C1P0 — SI2C1P2 SI2C1P1 SI2C1P0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CNI
PIC24F16KA102 FAMILY REGISTER 8-18: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 INT1IP<2:0>: External Interrupt 1 Priority bits 111 = Interrupt
PIC24F16KA102 FAMILY REGISTER 8-19: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — U2TXIP2 U2TXIP1 U2TXIP0 — U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — INT2IP2 INT2IP1 INT2IP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 U2TXIP<2:0>: UA
PIC24F16KA102 FAMILY REGISTER 8-20: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Priority bi
PIC24F16KA102 FAMILY REGISTER 8-21: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 — CRCIP2 CRCIP1 CRCIP0 — U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 — U1ERIP2 U1ERIP1 U1ERIP0 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplemented: Read as ‘0’ bit 14-12 CRCIP<2:0>: CRC
PIC24F16KA102 FAMILY REGISTER 8-22: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 — — — — — HLVDIP2 HLVDIP1 HLVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-3 Unimplemented: Read as ‘0’ bit 2-0 HLVDIP<2:0>: High/Low-Voltage Detect Interrupt Priority bits
PIC24F16KA102 FAMILY REGISTER 8-24: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER R-0 U-0 R/W-0 U-0 R-0 R-0 R-0 R-0 CPUIRQ — VHOLD — ILR3 ILR2 ILR1 ILR0 bit 15 bit 8 U-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 — VECNUM6 VECNUM5 VECNUM4 VECNUM3 VECNUM2 VECNUM1 VECNUM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CPUIRQ: Interrupt Request from Interru
PIC24F16KA102 FAMILY 8.4 Interrupt Setup Procedures 8.4.1 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source.
PIC24F16KA102 FAMILY 9.0 • Software-controllable switching between various clock sources. • Software-controllable postscaler for selective clocking of CPU for system power savings. • System frequency range declaration bits for EC mode. When using an external clock source, the current consumption is reduced by setting the declaration bits to the expected frequency range. • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown.
PIC24F16KA102 FAMILY 9.1 CPU Clocking Scheme 9.2 The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins The PIC24F16KA102 family devices consist of two types of secondary oscillator: - High-Power Secondary Oscillator - Low-Power Secondary Oscillator These can be selected by using the SOSCSEL (FOSC<5>) bit.
PIC24F16KA102 FAMILY 9.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers (SFRs): • OSCCON • CLKDIV • OSCTUN The OSCCON register (Register 9-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. REGISTER 9-1: The Clock Divider register (Register 9-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator.
PIC24F16KA102 FAMILY REGISTER 9-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.
PIC24F16KA102 FAMILY REGISTER 9-2: CLKDIV: CLOCK DIVIDER REGISTER R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-0 R/W-1 ROI DOZE2 DOZE1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and
PIC24F16KA102 FAMILY REGISTER 9-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 — U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as ‘0’ bit 5-0 TUN<5:0>: FRC Oscillator Tun
PIC24F16KA102 FAMILY 9.4 Clock Switching Operation With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: 9.4.1 The Primary Oscillator mode has three different submodes (XT, HS and EC), which are determined by the POSCMDx Configuration bits.
PIC24F16KA102 FAMILY The following code sequence for a clock switch is recommended: 1. 2. 3. 4. 5. 6. 7. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence.
PIC24F16KA102 FAMILY REGISTER 9-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference
PIC24F16KA102 FAMILY NOTES: DS39927C-page 100 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY 10.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 39. Power-Saving Features with Deep Sleep” (DS39727). The PIC24F16KA102 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals.
PIC24F16KA102 FAMILY 10.2.2 IDLE MODE Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 10.4 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active.
PIC24F16KA102 FAMILY 10.2.4.2 Exiting Deep Sleep Mode Deep Sleep mode exits on any one of the following events: • POR event on VDD supply. If there is no DSBOR circuit to re-arm the VDD supply POR circuit, the external VDD supply must be lowered to the natural arming voltage of the POR circuit. • DSWDT time-out. When the DSWDT timer times out, the device exits Deep Sleep. • RTCC alarm (if RTCEN = 1). • Assertion (‘0’) of the MCLR pin.
PIC24F16KA102 FAMILY 10.2.4.5 Deep Sleep WDT To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (FDS<7>). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. The DSWDT clock source is selected by the DSWDTOSC Configuration bit (FDS<4>). The postscaler options are programmed by the DSWDTPS<3:0> Configuration bits (FDS<3:0>). The minimum time-out period that can be achieved is 2.
PIC24F16KA102 FAMILY DSCON: DEEP SLEEP CONTROL REGISTER(1) REGISTER 10-1: R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 DSEN — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — U-0 — U-0 — U-0 — R/W-0 DSBOR (2) R/C-0, HS RELEASE bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 DSEN: Deep Sleep Enable bit 1 = Enters Deep
PIC24F16KA102 FAMILY DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER(1) REGISTER 10-2: U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS — — — — — — — DSINT0 bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0, HS R/W-0, HS R/W-0, HS U-0 R/W-0, HS DSFLT — — DSWDT DSRTCC DSMCLR — DSPOR(2,3) bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimpl
PIC24F16KA102 FAMILY 10.3 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else.
PIC24F16KA102 FAMILY REGISTER 10-3: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 — — T3MD T2MD T1MD — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 I2C1MD U2MD U1MD — SPI1MD — — ADC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as ‘0’ bit 13 T3MD: Timer3 Module Di
PIC24F16KA102 FAMILY REGISTER 10-4: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — I2C1MD bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — OC1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as ‘0’ bit 8 I2C1MD: Input Capture 1 Module Disable bit 1 = Input Capt
PIC24F16KA102 FAMILY REGISTER 10-5: PMD3: PERIPHERAL MODULE DISABLE REGISTER 3 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0 — — — — — CMPMD RTCCMD — bit 15 bit 8 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 CRCMD — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10 CMPMD: Comparator Module Disable bit 1 = Comparat
PIC24F16KA102 FAMILY REGISTER 10-6: PMD4: PERIPHERAL MODULE DISABLE REGISTER 4 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 — — — EEMD REFOMD CTMUMD HLVDMD — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 4 EEMD: EEPROM Memory Module Disable bit 1 = D
PIC24F16KA102 FAMILY NOTES: DS39927C-page 112 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY 11.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the I/O ports, refer to the “PIC24F Family Reference Manual”, Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). Note that the PIC24F16KA102 family devices do not support Peripheral Pin Select features.
PIC24F16KA102 FAMILY 11.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 11.
PIC24F16KA102 FAMILY 12.0 Note: Figure 12-1 presents a block diagram of the 16-bit Timer1 module. TIMER1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). To configure Timer1 for operation: 1. 2. 3. 4.
PIC24F16KA102 FAMILY REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 — TSYNC TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as
PIC24F16KA102 FAMILY 13.0 Note: TIMER2/3 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Timers, refer to the “PIC24F Family Reference Manual”, Section 14. “Timers” (DS39704). The Timer2/3 module is a 32-bit timer, which can also be configured as two independent 16-bit timers with selectable operating modes.
PIC24F16KA102 FAMILY FIGURE 13-1: TIMER2/3 (32-BIT) BLOCK DIAGRAM TCKPS<1:0> 2 TON T2CK 1x Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 TGATE TGATE TCS Q 1 Set T3IF Q 0 PR3 A/D Event Trigger Equal D CK PR2 Comparator MSB LSB TMR3 Reset TMR2 Sync 16 Read TMR2 (1) Write TMR2(1) 16 TMR3HLD 16 16 Data Bus<15:0> Note 1: DS39927C-page 118 The 32-Bit Timer Configuration (T32) bit must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON register.
PIC24F16KA102 FAMILY FIGURE 13-2: TIMER2 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TON T2CK TCKPS<1:0> 2 1x Gate Sync Prescaler 1, 8, 64, 256 01 00 TGATE TCS TCY 1 Set T2IF 0 Reset Equal Q D Q CK TGATE TMR2 Sync Comparator PR2 FIGURE 13-3: TIMER3 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM TON Sync T3CK TCKPS<1:0> 2 1x Prescaler 1, 8, 64, 256 01 00 TGATE TCY 1 Set T3IF 0 Reset A/D Event Trigger Equal Q D Q CK TCS TGATE TMR3 Comparator PR3 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY REGISTER 13-1: T2CON: TIMER2 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON — TSIDL — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 — TGATE TCKPS1 TCKPS0 T32(1) — TCS — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer2 On bit When T2CON<3> = 1: 1 = Starts 32-bit Timer2/3 0 = Stops 32-bit Timer2/3 When T2
PIC24F16KA102 FAMILY REGISTER 13-2: T3CON: TIMER3 CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) — TSIDL(1) — — — — — bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 — TGATE(1) TCKPS1(1) TCKPS0(1) — — TCS(1) — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 TON: Timer3 On bit(1) 1 = Starts 16-bit Timer3 0 = Stops 16-bit Timer3 bit 14 Unimple
PIC24F16KA102 FAMILY NOTES: DS39927C-page 122 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY 14.0 INPUT CAPTURE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Input Capture, refer to the “PIC24F Family Reference Manual”, Section 15. “Input Capture” (DS39701). The input capture module is used to capture a timer value from one of two selectable time bases upon an event on an input pin.
PIC24F16KA102 FAMILY 14.
PIC24F16KA102 FAMILY 15.0 Note: 15.1 OUTPUT COMPARE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Output Compare, refer to the “PIC24F Family Reference Manual”, Section 16. “Output Compare” (DS39706).
PIC24F16KA102 FAMILY 15.3 EQUATION 15-1: Pulse-Width Modulation (PWM) Mode PWM Period = [(PRy) + 1] • TCY • (Timer Prescale Value) where: PWM Frequency = 1/[PWM Period] The following steps should be taken when configuring the output compare module for PWM operation: 1. 2. 3. 4. 5. 6. Set the PWM period by writing to the selected Timer Period register (PRy). Set the PWM duty cycle by writing to the OC1RS register. Write the OC1R register with the initial duty cycle.
PIC24F16KA102 FAMILY EXAMPLE 15-1: 1. PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s PWM Period = (PR2 + 1) • TCY • (Timer 2 Prescale Value) 19.2 s = (PR2 + 1) • 62.5 ns • 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.
PIC24F16KA102 FAMILY FIGURE 15-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OC1IF(1) OC1RS(1) Output Logic OC1R(1) 3 OCM<2:0> Mode Select Comparator 0 16 OCTSEL 1 0 S Q R OC1(1) Output Enable OCFA(2) 1 16 TMR Register Inputs from Time Bases(3) Period Match Signals from Time Bases(3) Note 1: Where ‘x’ is depicted, reference is made to the registers associated with the respective Output Compare Channel 1. 2: OCFA pin controls OC1 channel.
PIC24F16KA102 FAMILY 15.
PIC24F16KA102 FAMILY REGISTER 15-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 U-0 U-0 — — U-0 — R/W-0 R/W-0 (3) SMBUSDEL R/W-0 (2) OC1TRIS R/W-0 (1,4) RTSECSEL1 R/W-0 (1,4) RTSECSEL0 bit 7 — bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as ‘0’ bit 3 OC1TRIS: OC1
PIC24F16KA102 FAMILY 16.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Serial Peripheral Interface, refer to the “PIC24F Family Reference Manual”, Section 23. “Serial Peripheral Interface (SPI)” (DS39699).
PIC24F16KA102 FAMILY FIGURE 16-1: SPI1 MODULE BLOCK DIAGRAM (STANDARD BUFFER MODE) SCK1 1:1 to 1:8 Secondary Prescaler SS1/FSYNC1 Sync Control 1:1/4/16/64 Primary Prescaler Select Edge Control Clock SPI1CON1<1:0> SPI1CON1<4:2> Shift Control SDO1 Enable Master Clock bit 0 SDI1 FCY SPI1SR Transfer Transfer SPI1BUF Read SPI1BUF Write SPI1BUF 16 Internal Data Bus DS39927C-page 132 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY To set up the SPI module for the Enhanced Buffer Master (EBM) mode of operation: To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the respective SPI1IF bit in the IFS0 register. b) Set the respective SPI1IE bit in the IEC0 register. c) Write the respective SPI1IPx bits in the IPC2 register. Write the desired settings to the SPI1CON1 and SPI1CON2 registers with the MSTEN bit (SPI1CON1<5>) = 1.
PIC24F16KA102 FAMILY REGISTER 16-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 R-0, HSC R-0, HSC R-0, HSC SPIEN — SPISIDL — — SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R-0,HSC R/C-0, HS R/W-0, HSC R/W-0 R/W-0 R/W-0 R-0, HSC R-0, HSC SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: U = Unimplemented bit, read as ‘0’ HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit H = Hardware Settable bit C = Clea
PIC24F16KA102 FAMILY REGISTER 16-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPI1 Transmit Buffer Full Status bit 1 = Transmit has not yet started, SPI1TXB is full 0 = Transmit has started, SPI1TXB is empty In Standard Buffer mode: Automatically set in hardware when the CPU writes to the SPITBF location, loading SPITBF. Automatically cleared in hardware when the SPI1 module transfers data from SPI1TXB to SPIRBF.
PIC24F16KA102 FAMILY REGISTER 16-2: SPI1CON1: SPI1 CONTROL REGISTER 1 U-0 — bit 15 U-0 — U-0 — R/W-0 DISSCK R/W-0 DISSDO R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(1) bit 8 R/W-0 SSEN bit 7 R/W-0 CKP R/W-0 MSTEN R/W-0 SPRE2 R/W-0 SPRE1 R/W-0 SPRE0 R/W-0 PPRE1 R/W-0 PPRE0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-2 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = B
PIC24F16KA102 FAMILY REGISTER 16-2: bit 1-0 Note 1: SPI1CON1: SPI1 CONTROL REGISTER 1 (CONTINUED) PPRE<1:0>: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 The CKE bit is not used in the Framed SPI modes. The user should program this bit to ‘0’ for the Framed SPI modes (FRMEN = 1).
PIC24F16KA102 FAMILY EQUATION 16-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FCY FSCK = Primary Prescaler * Secondary Prescaler Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled.
PIC24F16KA102 FAMILY 17.0 Note: INTER-INTEGRATED CIRCUIT (I2C™) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Inter-Integrated Circuit, refer to the “PIC24F Family Reference Manual”, Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS39702). 17.2 The details of sending a message in Master mode depends on the communications protocol for the device being communicated with.
PIC24F16KA102 FAMILY FIGURE 17-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2C1RCV SCL1 Read Shift Clock I2C1RSR LSB SDA1 Address Match Match Detect Write I2C1MSK Write Read I2C1ADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2C1STAT Collision Detect Read Write I2C1CON Acknowledge Generation Read Clock Stretching Write I2C1TRN LSB Read Shift Clock Reload Control BRG Down Counter Write I2C1BRG Read TCY/2 DS39927C-page 140 2008-2011 Microchip Tec
PIC24F16KA102 FAMILY 17.3 Setting Baud Rate When Operating as a Bus Master 17.4 The I2C1MSK register (Register 17-3) designates address bit positions as “don’t care” for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2C1MSK register causes the slave module to respond whether the corresponding address bit value is ‘0’ or ‘1’. For example, when I2C1MSK is set to ‘00100000’, the slave module will detect both addresses: ‘0000000’ and ‘00100000’.
PIC24F16KA102 FAMILY REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit
PIC24F16KA102 FAMILY REGISTER 17-1: I2C1CON: I2C1 CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master; applicable during master receive) Value that will be transmitted when the software initiates an Acknowledge sequence.
PIC24F16KA102 FAMILY REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS IWCOL I2COV R-0, HSC R/C-0, HSC R/C-0, HSC D/A P R-0, HSC R-0, HSC R-0, HSC R/W RBF TBF S bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value a
PIC24F16KA102 FAMILY REGISTER 17-2: I2C1STAT: I2C1 STATUS REGISTER (CONTINUED) bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware is set or clear when Start, Repeated Start or Stop is detected.
PIC24F16KA102 FAMILY REGISTER 17-3: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 — — — — — — AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as ‘0’ bit 9-0 AMS
PIC24F16KA102 FAMILY 18.0 Note: UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Universal Asynchronous Receiver Transmitter, refer to the “PIC24F Family Reference Manual”, Section 21. “UART” (DS39708). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in this PIC24F device family.
PIC24F16KA102 FAMILY 18.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator (BRG). The UxBRG register controls the period of a free-running, 16-bit timer. Equation 18-1 provides the formula for computation of the baud rate with BRGH = 0. EQUATION 18-1: Baud Rate = The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536).
PIC24F16KA102 FAMILY 18.2 1. 2. 3. 4. 5. 6. Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write data byte to lower byte of UxTXREG word.
PIC24F16KA102 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0(2) R/W-0(2) UARTEN — USIDL IREN(1) RTSMD — UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x
PIC24F16KA102 FAMILY REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL<1:0>: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1:
PIC24F16KA102 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0, HC R/W-0 R-0, HSC R-1, HSC UTXISEL1 UTXINV UTXISEL0 — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1, HSC R-0, HSC R-0, HSC R/C-0, HS R-0, HSC URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 HC = Hardware Clearable bit Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit R = Readable bit W = Writabl
PIC24F16KA102 FAMILY REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled. If 9-bit mode is not selected, this does not take effect.
PIC24F16KA102 FAMILY REGISTER 18-3: UxTXREG: UARTx TRANSMIT REGISTER U-x — bit 15 U-x — U-x — U-x — U-x — U-x — U-x — W-x UTX8 bit 8 W-x UTX7 bit 7 W-x UTX6 W-x UTX5 W-x UTX4 W-x UTX3 W-x UTX2 W-x UTX1 W-x UTX0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 bit 7-0 U-0 — bit 15 UxRXREG: UARTx RECEIVE REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0, HSC URX8 bit 8 R-0, HSC URX6 R-0, HSC URX5 R-0, HSC URX4 R-0, HSC URX3 R-0, HSC URX2 R-0, HSC URX1 R-0, HSC UR
PIC24F16KA102 FAMILY 19.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Real-Time Clock and Calendar, refer to the “PIC24F Family Reference Manual”, Section 29. “Real-Time Clock and Calendar (RTCC)” (DS39696). The RTCC provides the user with a Real-Time Clock and Calendar (RTCC) function that can be calibrated.
PIC24F16KA102 FAMILY 19.2 TABLE 19-2: RTCC Module Registers The RTCC module registers are organized into three categories: ALRMPTR <1:0> • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers 19.2.1 00 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers.
PIC24F16KA102 FAMILY 19.2.
PIC24F16KA102 FAMILY REGISTER 19-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 Note 1: 2: 3: CAL<7:0>: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute . . .
PIC24F16KA102 FAMILY REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 ALRMEN bit 15 R/W-0 CHIME R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0 ALRMPTR1 R/W-0 ARPT7 bit 7 R/W-0 ARPT6 R/W-0 ARPT5 R/W-0 ARPT4 R/W-0 ARPT3 R/W-0 ARPT2 R/W-0 ARPT1 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9-8 bit 7-0 W = Writable bit ‘1’ = Bit is set R/W-0 ALRMPTR0 bit 8 R/W-0 ARPT0 bit 0 U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is un
PIC24F16KA102 FAMILY 19.2.
PIC24F16KA102 FAMILY REGISTER 19-6: WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x — — — — — WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — — HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as ‘0’ bit 10-8 WDAY<
PIC24F16KA102 FAMILY 19.2.
PIC24F16KA102 FAMILY REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x — SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 Unimplem
PIC24F16KA102 FAMILY 19.3 Calibration The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute.
PIC24F16KA102 FAMILY FIGURE 19-2: ALARM MASK SETTINGS Alarm Mask Setting (AMASK<3:0>) Day of the Week Month Day Hours Minutes Seconds 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds s 0011 - Every minute s s m s s m m s s 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week d 1000 - Every month 1001 - Every year(1) m m h h m m s s h h m m s s d d h h m m s s d d h h m m s s Note 1: Annually, except when config
PIC24F16KA102 FAMILY NOTES: DS39927C-page 166 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY 20.0 The programmable CRC generator offers the following features: PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR Note: • User-programmable polynomial CRC equation • Interrupt output • Data FIFO This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on Programmable Cyclic Redundancy Check, refer to the “PIC24F Family Reference Manual”, Section 30.
PIC24F16KA102 FAMILY CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1 FIGURE 20-2: XOR D Q D Q D Q D Q D Q SDOx BIT 0 BIT 4 BIT 5 BIT 12 BIT 15 clk clk clk clk clk CRC Read Bus CRC Write Bus 20.1 20.1.1 User Interface DATA INTERFACE To start serial shifting, a value of ‘1’ must be written to the CRCGO bit. The module incorporates a FIFO that is 8-level deep when PLEN<3:0> > 7 and 16-deep, otherwise. The data for which the CRC is to be calculated must first be written into the FIFO.
PIC24F16KA102 FAMILY 20.
PIC24F16KA102 FAMILY REGISTER 20-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X15 X14 X13 X12 X11 X10 X9 X8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X7 X6 X5 X4 X3 X2 X1 — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-1 X<15:1>: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as ‘0’
PIC24F16KA102 FAMILY 21.0 An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. HIGH/LOW-VOLTAGE DETECT (HLVD) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source.
PIC24F16KA102 FAMILY REGISTER 21-1: HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 HLVDEN — HLSIDL — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 VDIR BGVST IRVST — HLVDL3 HLVDL2 HLVDL1 HLVDL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 HLVDEN: High/Low-Voltage Detect Power Ena
PIC24F16KA102 FAMILY 22.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the 10-Bit High-Speed A/D Converter, refer to the “PIC24F Family Reference Manual”, Section 17. “10-Bit A/D Converter” (DS39705). A block diagram of the A/D Converter is displayed in Figure 22-1. To perform an A/D conversion: 1.
PIC24F16KA102 FAMILY FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD VREF+ VR Select VR+ AVSS 16 VR- VREF- Comparator VINH VINL S/H VR- VR+ DAC 10-Bit SAR VINH Conversion Logic MUX A AN0 AN1 AN2 Data Formatting AN1 AN3 VINL ADC1BUF0: ADC1BUFF AN4 AN5 AD1CON1 AN10 AD1CON2 AN11 AD1CON3 AD1CHS MUX B AN12 VBG VBG/2 AN1 VINH AD1PCFG AD1CSSL VINL Sample Control Control Logic Conversion Control Input MUX Control Pin Config Control DS39927C-page 1
PIC24F16KA102 FAMILY REGISTER 22-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) — ADSIDL — — — FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HSC R/W-0, HSC SSRC2 SSRC1 SSRC0 — — ASAM SAMP DONE bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: A/
PIC24F16KA102 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 OFFCAL(1) — CSCNA — — bit 15 bit 8 R-0, HSC U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: HSC = Hardware Settable/Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 x = Bit is unknown
PIC24F16KA102 FAMILY REGISTER 22-2: AD1CON2: A/D CONTROL REGISTER 2 (CONTINUED) bit 1 BUFM: Buffer Mode Select bit 1 = Buffer is configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>) 0 = Buffer is configured as one 16-word buffer (ADC1BUFn<15:0>) bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer s
PIC24F16KA102 FAMILY - REGISTER 22-4: AD1CHS: A/D INPUT SELECT REGISTER R/W-0 CH0NB bit 15 U-0 — U-0 — U-0 — R/W-0 CH0SB3 R/W-0 CH0SB2 R/W-0 CH0SB1 R/W-0 CH0SB0 bit 8 R/W-0 CH0NA bit 7 U-0 — U-0 — U-0 — R/W-0 CH0SA3 R/W-0 CH0SA2 R/W-0 CH0SA1 R/W-0 CH0SA0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CH0NB: Channel 0 Negative
PIC24F16KA102 FAMILY REGISTER 22-5: AD1PCFG: A/D PORT CONFIGURATION REGISTER R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 PCFG15 PCFG14 — PCFG12 PCFG11 PCFG10 — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 PCFG15: Analog Input Pin Configuration
PIC24F16KA102 FAMILY REGISTER 22-6: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW) U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 — — — CSSL12 CSSL11 CSSL10 — — bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15-13 Unimplemented: Read as ‘0’ bit 12-10 CSSL<12:10>: A/D Input Pi
PIC24F16KA102 FAMILY EQUATION 22-1: A/D CONVERSION CLOCK PERIOD(1) TAD ADCS = TCY – 1 TAD = TCY • (ADCS + 1) Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA RIC 250 VT = 0.6V ANx CPIN 6-11 pF (Typical) VT = 0.6V Sampling Switch RSS 5 k (Typical) RSS ILEAKAGE ±500 nA CHOLD = A/D capacitance = 4.
PIC24F16KA102 FAMILY FIGURE 22-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) DS39927C-page 182 (VINH – VINL) VR+ 1023 * (VR+ – VR-) 1024 VR- + 512 * (VR+ – VR-) 1024 VR- + VR- + VR+ – VR1024 0 Voltage Level VR- 00 0000 0000 (0) 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY 23.0 The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. COMPARATOR MODULE Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator module, refer to the “PIC24F Family Reference Manual”, Section 46.
PIC24F16KA102 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH<1:0> = xx VIN- COE - VIN+ Cx Off (Read as ‘0’) Comparator CxINB < CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 00 CXINB CXINA VIN- Comparator CxINC < CxINA Compare CON = 1, CREF = 0, CCH<1:0> = 01 COE - CXINC Cx VIN+ CxOUT Pin CXINA VIN- COE - VBG/2 Cx VIN+ CxOUT Pin Comparator CxINB < CVREF Compare CON = 1, CREF = 1, CCH<1:0> = 00 CXINB CVREF VIN- CVREF DS39927C-page 184
PIC24F16KA102 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R-0 CON COE CPOL CLPWR — — CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 — CREF — — CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 CON: Comparator Enable bit 1 = Comparator is enabled 0
PIC24F16KA102 FAMILY REGISTER 23-1: CMxCON: COMPARATOR x CONTROL REGISTERS (CONTINUED) bit 5 Unimplemented: Read as ‘0’ bit 4 CREF: Comparator Reference Select bit (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CxINA pin bit 3-2 Unimplemented: Read as ‘0’ bit 1-0 CCH<1:0>: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG/2 10 = Inverting input of comparator connects to CxIND pin 01 = Inver
PIC24F16KA102 FAMILY 24.0 Note: COMPARATOR VOLTAGE REFERENCE 24.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>).
PIC24F16KA102 FAMILY REGISTER 24-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as ‘0’ bit 7 CVREN: Comparato
PIC24F16KA102 FAMILY 25.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Charge Measurement Unit, refer to the “PIC24F Family Reference Manual”, Section 11. “Charge Time Measurement Unit (CTMU)” (DS39724).
PIC24F16KA102 FAMILY 25.2 When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON<12>), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected.
PIC24F16KA102 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 15 CTMUEN: CTMU Enabl
PIC24F16KA102 FAMILY REGISTER 25-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL<1:0>: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred REGISTER 25-2: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITR
PIC24F16KA102 FAMILY 26.0 SPECIAL FEATURES Note: 26.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Watchdog Timer, High-Level Device integration and Programming Diagnostics, refer to the individual sections of the “PIC24F Family Reference Manual” provided below: • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 36.
PIC24F16KA102 FAMILY REGISTER 26-2: FGS: GENERAL SEGMENT CONFIGURATION REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — GSS0 GWRP bit 7 bit 0 Legend: R = Readable bit C = Clearable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 Unimplemented: Read as ‘0’ bit 1 GSS0: General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security is enabled bit 0 GWRP: General Segment Code Flash Write Protect
PIC24F16KA102 FAMILY REGISTER 26-4: FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-1 R/P-1 FCKSM1 FCKSM0 R/P-1 R/P-1 R/P-1 R/P-1 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC R/P-1 R/P-1 POSCMD1 POSCMD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock M
PIC24F16KA102 FAMILY REGISTER 26-5: FWDT: WATCHDOG TIMER CONFIGURATION REGISTER R/P-1 R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 FWDTEN WINDIS — FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 FWDTEN: Watchdog Timer Enable bit 1 = WDT is enabled 0 = WDT is disabled (control is placed on the SWDTEN bit) bit 6 WINDIS: Windowed Watchdog Timer Dis
PIC24F16KA102 FAMILY REGISTER 26-6: FPOR: RESET CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-0 R/P-1 R/P-1 MCLRE(2) BORV1(3) BORV0(3) I2C1SEL(1) PWRTEN — BOREN1 BOREN0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit(2) 1 = MCLR pin is enabled; RA5 input pin is disabled 0 = RA5 input pin is enabled; MCLR is disabled bit
PIC24F16KA102 FAMILY REGISTER 26-7: FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER R/P-1 U-0 U-0 U-0 U-0 U-0 R/P-1 R/P-1 DEBUG — — — — — FICD1 FICD0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit 1 = Background debugger is disabled 0 = Background debugger functions are enabled bit 6-2 Unimplemented: Read as ‘0’ b
PIC24F16KA102 FAMILY REGISTER 26-8: FDS: DEEP SLEEP CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 DSWDTEN DSBOREN RTCOSC R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT is enabled 0 = DSWDT is disabled bit 6 DSBOREN: Deep Sleep/Low-Po
PIC24F16KA102 FAMILY REGISTER 26-9: DEVID: DEVICE ID REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 23 bit 16 R R R R R R R R FAMID7 FAMID6 FAMID5 FAMID4 FAMID3 FAMID2 FAMID1 FAMID0 bit 15 bit 8 R R R R R R R R DEV7 DEV6 DEV5 DEV4 DEV3 DEV2 DEV1 DEV0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 23-16 Unimplemented: Read as ‘0’ bit
PIC24F16KA102 FAMILY 26.2 Watchdog Timer (WDT) For the PIC24F16KA102 family of devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit.
PIC24F16KA102 FAMILY 26.3 Deep Sleep Watchdog Timer (DSWDT) In PIC24F16KA102 family devices, in addition to the WDT module, a DSWDT module is present which runs while the device is in Deep Sleep, if enabled. It is driven by either the SOSC or LPRC oscillator. The clock source is selected by the Configuration bit, DSWDTOSC (FDS<4>). The DSWDT can be configured to generate a time-out at 2.1 ms to 25.7 days by selecting the respective postscaler.
PIC24F16KA102 FAMILY 27.0 DEVELOPMENT SUPPORT 27.
PIC24F16KA102 FAMILY 27.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 27.
PIC24F16KA102 FAMILY 27.7 MPLAB SIM Software Simulator 27.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC24F16KA102 FAMILY 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC24F16KA102 FAMILY 28.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations.
PIC24F16KA102 FAMILY TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by “text” (text) Means “content of text” [text] Means “the location addressed by text” { } Optional field or operation Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...
PIC24F16KA102 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C, D
PIC24F16KA102 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax # of Words Description # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws to C 1 1 C Z BTST.
PIC24F16KA102 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 Ws,
PIC24F16KA102 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None
PIC24F16KA102 FAMILY TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR.
PIC24F16KA102 FAMILY NOTES: DS39927C-page 214 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24F16KA102 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24F16KA102 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability.
PIC24F16KA102 FAMILY 29.1 DC Characteristics Voltage (VDD) FIGURE 29-1: PIC24F16KA102 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.60V 3.60V 3.00V 3.00V 1.80V 0 0 8 MHz 16 MHz 24 MHz 32 MHz Frequency (MHz) Note: For Industrial temperatures, for frequencies between 8 MHz and 32 MHz, FMAX = (20 MHz/V) * (VDD – 1.8V) + 8 MHz. Voltage (VDD) FIGURE 29-2: PIC24F16KA102 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 3.60V 3.60V 3.00V 3.00V 1.
PIC24F16KA102 FAMILY TABLE 29-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 — +175 °C Operating Ambient Temperature Range TA -40 — +125 °C Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – IOH) PD PINT + PI/O W PDMAX (TJ – TA)/JA W I/O Pin Power Dissipation: PI/O = ({VDD – VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS Characteristic
PIC24F16KA102 FAMILY TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param Symbol No. Characteristic Min Typ(1) Max Units DC10 VDD Supply Voltage 1.8 — 3.6 V DC12 VDR RAM Data Retention Voltage(2) 1.5 — — V DC16 VPOR VDD Start Voltage to Ensure Internal Power-on Reset Signal VSS — 0.
PIC24F16KA102 FAMILY FIGURE 29-3: BROWN-OUT RESET CHARACTERISTICS VDDCORE (Device not in Brown-out Reset) BO15 BO10 (Device in Brown-out Reset) SY25 Reset (Due to BOR) TABLE 29-5: TVREG + TRST BOR TRIP POINTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +85°C for industrial -40°C TA +125°C for Extended Param No. DC19 DC14 Sym VBOR VBHYS Note 1: Characteristic Min Typ BOR Voltage on VDD Transition BOR = 00 — — — — BOR = 01 2.92 3 3.
PIC24F16KA102 FAMILY TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No.
PIC24F16KA102 FAMILY TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. IDD Current(2) DC31 DC31a DC31b DC31c DC31d DC31e DC31f DC31g DC31h Note 1: 2: Typical(1) 8 Max 28 28 28 28 55 Units A Conditions -40°C +25°C +60°C +85°C -40°C 1.8V LPRC (31 kHz) 55 +25°C 15 55 A +60°C 3.
PIC24F16KA102 FAMILY TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Typical(1) Max Units Conditions (2) Idle Current (IIDLE): Core Off, Clock on Base Current, PMD Bits are Set DC40 100 -40°C DC40a 100 +25°C DC40b 100 +60°C 48 A 1.8V DC40c 100 +85°C DC40d 100 +125°C 0.
PIC24F16KA102 FAMILY TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Typical(1) Max Units Conditions (2) Idle Current (IIDLE): Core Off, Clock on Base Current, PMD Bits are Set DC50 18 -40°C DC50a 18 +25°C 2 1.
PIC24F16KA102 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC60 0.200 -40°C DC60a 0.200 +25°C DC60b 0.025 0.870 A +60°C DC60c 1.350 +85°C DC60d 10.00 +125°C DC60e 0.
PIC24F16KA102 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC62 0.650 -40°C DC62a 0.650 +25°C DC62b 0.450 0.650 A +60°C DC62c 0.650 +85°C DC62d — +125°C DC62e 0.
PIC24F16KA102 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) DC70 0.200 -40°C DC70a 0.200 +25°C DC70b 0.045 DC70c 0.200 A +60°C 0.200 +85°C DC70d 1.45 +125°C DC70e 0.
PIC24F16KA102 FAMILY TABLE 29-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended DC CHARACTERISTICS Param No. Sym VIL Characteristic Input Low Voltage(4) Min Typ(1) Max Units — — — — DI10 I/O Pins VSS — 0.2 VDD V DI15 MCLR VSS — 0.2 VDD V DI16 OSCI (XT mode) VSS — 0.2 VDD V DI17 OSCI (HS mode) VSS — 0.
PIC24F16KA102 FAMILY TABLE 29-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. Sym VOL Characteristic All I/O Pins DO16 OSC2/CLKO VOH DO26 Note 1: Min Typ(1) Max Units — — 0.4 V — — 0.4 V IOL = 3.5 mA, VDD = 2.0V — — 0.4 V IOL = 8.0 mA, VDD = 3.6V — — 0.4 V IOL = 4.5 mA, VDD = 1.8V Conditions Output Low Voltage DO10 DO20 Standard Operating Conditions: 1.8V to 3.
PIC24F16KA102 FAMILY TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min Typ(1) 10,000(2) VMIN Max Units — — E/W — 3.
PIC24F16KA102 FAMILY TABLE 29-13: COMPARATOR DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Param No. Symbol Characteristic Min Typ Max Units D300 VIOFF Input Offset Voltage* — 20 40 mV D301 VICM Input Common Mode Voltage* 0 — VDD V D302 CMRR Common Mode Rejection Ratio* 55 — — dB Comments * Parameters are characterized but not tested.
PIC24F16KA102 FAMILY 29.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24F16KA102 family AC characteristics and timing parameters. TABLE 29-17: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Operating voltage VDD range as described in Section 29.1 “DC Characteristics”.
PIC24F16KA102 FAMILY FIGURE 29-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS31 OS30 OS31 OS25 CLKO OS40 OS41 TABLE 29-19: EXTERNAL CLOCK TIMING REQUIREMENTS Standard Operating Conditions: 1.8 to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Sym No.
PIC24F16KA102 FAMILY TABLE 29-20: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 3.6V) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC24F16KA102 FAMILY TABLE 29-22: AC SPECIFICATIONS Symbol Characteristics TLW BCLKx High Time Min Typ Max Units 20 TCY/2 — ns THW BCLKx Low Time 20 (TCY * BRGx) + TCY/2 — ns TBLD BCLKx Falling Edge Delay from UxTX -50 — 50 ns TCY/2 – 50 — TCY/2 + 50 ns — 1 — s TCY — — ns 3 — — ns — — TCY + TSETUP ns TBHD BCLKx Rising Edge Delay from UxTX TWAK Min. Low on UxRX Line to Cause Wake-up TCTS Min.
PIC24F16KA102 FAMILY TABLE 29-24: A/D MODULE SPECIFICATIONS A/D CHARACTERISTICS Param No. Symbol Characteristic Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 1.8 — Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS – 0.3 — VSS + 0.
PIC24F16KA102 FAMILY FIGURE 29-6: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 29-4 for load conditions. TABLE 29-25: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 1.8V to 3.
PIC24F16KA102 FAMILY TABLE 29-26: COMPARATOR TIMINGS Param No. Symbol Characteristic Min Typ Max Units 300 TRESP Response Time*(1) — 150 400 ns 301 TMC2OV Comparator Mode Change to Output Valid* — — 10 s * Note 1: Comments Parameters are characterized but not tested. Response time is measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 29-27: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Param No.
PIC24F16KA102 FAMILY FIGURE 29-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS VDD MCLR SY12 SY10 Internal POR PWRT SY11 SYSRST System Clock Watchdog Timer Reset SY20 SY13 SY13 I/O Pins SY35 DS39927C-page 238 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY TABLE 29-28: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No. Characteristic Min. Typ(1) Max.
PIC24F16KA102 FAMILY I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) FIGURE 29-9: SCLx IM31 IM34 IM30 IM33 SDAx Stop Condition Start Condition Note: Refer to Figure 29-4 for load conditions. TABLE 29-29: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial) -40°C TA +125°C for Extended AC CHARACTERISTICS Param Symbol No.
PIC24F16KA102 FAMILY TABLE 29-30: I2C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C for Industrial -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC24F16KA102 FAMILY I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) FIGURE 29-11: SCLx IS34 IS31 IS30 IS33 SDAx Stop Condition Start Condition FIGURE 29-12: I2C™ BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS11 IS21 IS10 SCLx IS25 IS20 IS26 SDAx In IS45 IS40 SDAx Out TABLE 29-31: I2C™ BUS START/STOP BIT TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.
PIC24F16KA102 FAMILY TABLE 29-32: I2C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +85°C (Industrial) -40°C TA +125°C for Extended AC CHARACTERISTICS Param No. IS10 IS11 IS20 IS21 Symbol TLO:SCL THI:SCL TF:SCL TR:SCL Characteristic Clock Low Time Clock High Time SDAx and SCLx Fall Time SDAx and SCLx Rise Time Min Max Units 100 kHz mode 4.7 — s Device must operate at a minimum of 1.
PIC24F16KA102 FAMILY FIGURE 29-14: INPUT CAPTURE TIMINGS ICx pin (Input Capture Mode) IC10 IC11 IC15 TABLE 29-33: INPUT CAPTURE Param. Symbol No.
PIC24F16KA102 FAMILY FIGURE 29-16: PWM MODULE TIMING REQUIREMENTS OC20 OCFx OC15 PWM TABLE 29-35: PWM TIMING REQUIREMENTS Param. Symbol No. Characteristic Min Typ† Max Units Conditions OC15 TFD Fault Input to PWM I/O Change — — 25 ns VDD = 3.0V, -40C to +125C OC20 TFH Fault Input Pulse Width 50 — — ns VDD = 3.0V, -40C to +125C † Data in “Typ” column is at 5V, 25C unless otherwise stated. These parameters are for design guidance only and are not tested.
PIC24F16KA102 FAMILY FIGURE 29-17: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 0) SCKx (CKP = 0) SP11 SP10 SP21 SP20 SP20 SP21 SCKx (CKP = 1) SP35 Bit 14 - - - - - -1 MSb SDOx SP31 SDIx LSb SP30 MSb In LSb In Bit 14 - - - -1 SP40 SP41 TABLE 29-36: SPIx MASTER MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C TA +125°C for Extended AC CHARACTERISTICS Param No.
PIC24F16KA102 FAMILY FIGURE 29-18: SPIx MODULE MASTER MODE TIMING CHARACTERISTICS (CKE = 1) SP36 SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP10 SP21 SP20 SP20 SP21 SP35 MSb SDOx SP40 SDIx Bit 14 - - - - - -1 LSb SP30,SP31 MSb In Bit 14 - - - -1 LSb In SP41 TABLE 29-37: SPIx MODULE MASTER MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.
PIC24F16KA102 FAMILY FIGURE 29-19: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 0) SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 MSb SDOx LSb Bit 14 - - - - - -1 SP51 SP30,SP31 SDIx SDI MSb In Bit 14 - - - -1 LSb In SP41 SP40 TABLE 29-38: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 0) Standard Operating Conditions: 2.0V to 3.
PIC24F16KA102 FAMILY FIGURE 29-20: SPIx MODULE SLAVE MODE TIMING CHARACTERISTICS (CKE = 1) SP60 SSx SP52 SP50 SCKx (CKP = 0) SP71 SP70 SP73 SP72 SP72 SP73 SCKx (CKP = 1) SP35 SP52 MSb SDOx Bit 14 - - - - - -1 LSb SP51 SP30,SP31 SDIx MSb In LSb In Bit 14 - - - -1 SP41 SP40 TABLE 29-39: SPIx MODULE SLAVE MODE TIMING REQUIREMENTS (CKE = 1) Standard Operating Conditions: 2.0V to 3.
PIC24F16KA102 FAMILY NOTES: DS39927C-page 250 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY 30.0 PACKAGING INFORMATION 30.1 Package Marking Information 20-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example 28-Lead SPDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP PIC24F16KA102 -I/SP e3 1110017 Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC24F16KA 101-I/SS e3 1110017 28-Lead SSOP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...
PIC24F16KA102 FAMILY 20-Lead SOIC (.300”) Example XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX PIC24F16KA101 -I/SO e3 YYWWNNN 1110017 28-Lead SOIC (.300”) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 20-Lead QFN XXXXXX XXXXXX XXXXXX YYWWNNN 28-Lead QFN XXXXXXXX XXXXXXXX YYWWNNN DS39927C-page 252 Example PIC24F16KA102 -I/SO e3 1110017 Example PIC24F 16KA101 -I/MQ e3 1110017 Example 24F16KA 102-I/ML e3 1110017 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY 30.2 Package Details The following sections give the technical details of the packages.
PIC24F16KA102 FAMILY /HDG 6NLQQ\ 3ODVWLF 'XDO ,Q /LQH 63 ± PLO %RG\ >63',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RS WR 6HDWLQJ 3ODQH $ ± ± 0ROGHG 3DFNDJH 7KLFNQHVV $ %DVH WR 6HDWLQJ 3ODQH $ ± ± 6KRXOGHU WR 6KRXOGHU :LGWK
PIC24F16KA102 FAMILY /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 e b c A2 A φ A1 L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV L 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO :LGWK ( 0
PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 256 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY /HDG 3ODVWLF 6KULQN 6PDOO 2XWOLQH 66 ± PP %RG\ >6623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 1 2 NOTE 1 b e c A2 A φ A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ ± %6& ± 0ROGHG 3DFNDJH 7KLFNQHVV $ 6WDQGRII $ ± ± 2YHUDOO :LGWK ( 0
PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 258 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 260 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 262 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 264 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY 20-Lead Plastic Quad Flat, No Lead Package (MQ) 5x5x0.9 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Microchip Technology Drawing C04-120A 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39927C-page 266 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D2 EXPOSED PAD e E b E2 2 2 1 1 N K N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ 6WDQGRII $ &RQWDFW
PIC24F16KA102 FAMILY /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS39927C-page 268 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY APPENDIX A: REVISION HISTORY Revision A (November 2008) Original data sheet for the PIC24F16KA102 family of devices. Revision B (March 2009) Section 29.0 “Electrical Characteristics” was revised and minor text edits were made throughout the document. Revision C (October 2011) • • • • • • • • • • • • • • • • • • • • • • • • • • • • • Changed all instances of DSWSRC to DSWAKE. Corrected Example 5-2. Corrected Example 5-4. Corrected Example 6-1. Corrected Example 6-3.
PIC24F16KA102 FAMILY NOTES: DS39927C-page 270 2008-2011 Microchip Technology Inc.
PIC24F16KA102 FAMILY INDEX A A/D 10-Bit High-Speed A/D Converter ............................ 173 A/D Characteristics Conversion Timing Requirements ............................ 234 Module Specifications .............................................. 235 A/D Converter Analog Input Model .................................................. 181 Transfer Function ..................................................... 182 AC Characteristics Capacitive Loading Requirements on Output Pins ...........................
PIC24F16KA102 FAMILY D Data EEPROM Bulk Erase .................................................................. 55 Erasing ....................................................................... 54 Operations ................................................................. 53 Programming Reading Data EEPROM .................................... 56 Single-Word Write .............................................. 55 Data Memory Address Space ...........................................................
PIC24F16KA102 FAMILY M Microchip Internet Web Site ............................................. 275 MPLAB ASM30 Assembler, Linker, Librarian .................. 204 MPLAB Integrated Development Environment Software .............................................. 203 MPLAB PM3 Device Programmer ................................... 206 MPLAB REAL ICE In-Circuit Emulator System ................ 205 MPLINK Object Linker/MPLIB Object Librarian ............... 204 N Near Data Space ................................
PIC24F16KA102 FAMILY IPC2 (Interrupt Priority Control 2) .............................. 81 IPC3 (Interrupt Priority Control 3) .............................. 82 IPC4 (Interrupt Priority Control 4) .............................. 83 IPC5 (Interrupt Priority Control 5) .............................. 84 IPC7 (Interrupt Priority Control 7) .............................. 85 MINSEC (RTCC Minutes and Seconds Value) ........ 161 MTHDY (RTCC Month and Day Value) ................... 160 NVMCON (Flash Memory Control) .
PIC24F16KA102 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers.
PIC24F16KA102 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC24F16KA102 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 F 16 KA1 02 T - I / PT - XXX Examples: a) Microchip Trademark Architecture PIC24F16KA102-I/ML: General purpose, 16-Kbyte program memory, 28-pin, Industrial temp., QFN package.
Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.
