Datasheet

PIC24F16KL402 FAMILY

DS30001037C-page 98  2011-2013 Microchip Technology Inc.

bit 7 CLKLOCK: Clock Selection Lock Enable bit

If FSCM is Enabled (FCKSM1 = 1):

1 = Clock and PLL selections are locked

0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit

If FSCM is Disabled (FCKSM1 =

0):

Clock and PLL selections are never locked and may be modified by setting the OSWEN bit.

bit 6 Unimplemented: Read as ‘0’

bit 5 LOCK: PLL Lock Status bit

(2)

1 = PLL module is in lock or the PLL module start-up timer is satisfied

0 = PLL module is out of lock, the PLL start-up timer is running or PLL is disabled

bit 4 Unimplemented: Read as ‘0’

bit 3 CF: Clock Fail Detect bit

1 = FSCM has detected a clock failure

0 = No clock failure has been detected

bit 2 SOSCDRV: Secondary Oscillator Drive Strength bit

(3)

1 = High-power SOSC circuit is selected

0 = Low/high-power select is done via the SOSCSRC Configuration bit

bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit

1 = Enables secondary oscillator

0 = Disables secondary oscillator

bit 0 OSWEN: Oscillator Switch Enable bit

1 = Initiates an oscillator switch to the clock source specified by the NOSC<2:0> bits

0 = Oscillator switch is complete

Note 1: Reset values for these bits are determined by the FNOSC<2:0> Configuration bits.

2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected.

3: When SOSC is selected to run from a digital clock input rather than an external crystal (SOSCSRC = 0),

this bit has no effect.