Datasheet

2011-2013 Microchip Technology Inc. DS30001037C-page 95
PIC24F16KL402 FAMILY
9.0 OSCILLATOR
CONFIGURATION
The oscillator system for the PIC24F16KL402 family of
devices has the following features:
A total of five external and internal oscillator options
as clock sources, providing 11 different clock
modes.
On-chip, 4x Phase Locked Loop (PLL) to boost
internal operating frequency on select internal and
external oscillator sources.
Software-controllable switching between various
clock sources.
Software-controllable postscaler for selective
clocking of CPU for system power savings.
System frequency range declaration bits for EC
mode. When using an external clock source, the
current consumption is reduced by setting the
declaration bits to the expected frequency range.
A Fail-Safe Clock Monitor (FSCM) that detects clock
failure and permits safe application recovery or
shutdown.
A simplified diagram of the oscillator system is shown in
Figure 9-1.
FIGURE 9-1: PIC24F16KL402 FAMILY CLOCK DIAGRAM
Note: This data sheet summarizes the features
of this group of PIC24F devices. It is not
intended to be a comprehensive refer-
ence source. For more information on
Oscillator Configuration, refer to the
“dsPIC33/PIC24 Family Reference
Manual, “Oscillator with 500 kHz
Low-Power FRC (DS39726).
Secondary Oscillator
SOSCEN
Enable
Oscillator
SOSCO
SOSCI
Clock Source Option
for Other Modules
OSCI
OSCO
Primary Oscillator
XT, HS, EC
Postscaler
CLKDIV<10:8>
WDT, PWRT, DSWDT
FRCDIV
31 kHz (nominal)
8 MHz
FRC
LPRC
Oscillator
SOSC
LPRC
Clock Control Logic
Fail-Safe
Clock
Monitor
FRC
4 x PLL
8 MHz
4 MHz
CPU
Peripherals
Postscaler
CLKDIV<14:12>
CLKO
Reference Clock
Generator
REFO
REFOCON<15:8>
Oscillator
500 kHz
LPFRC
Oscillator
XTPLL, HSPLL,
ECPLL, FRCPLL