Datasheet

PIC24F16KL402 FAMILY
DS30001037C-page 90  2011-2013 Microchip Technology Inc.
REGISTER 8-26: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12
U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0
— — — — — BCL2IP2
(1)
BCL2IP1
(1)
BCL2IP0
(1)
bit 15 bit 8
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0
— SSP2IP2
(1)
SSP2IP1
(1)
SSP2IP0
(1)
— — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-11 Unimplemented: Read as ‘0’
bit 10-8 BCL2IP<2:0>: MSSP2 I
2
C™ Bus Collision Interrupt Priority bits
(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 7 Unimplemented: Read as ‘0’
bit 6-4 SSP2IP<2:0>: MSSP2 SPI/I
2
C Event Interrupt Priority bits
(1)
111 = Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001 = Interrupt is Priority 1
000 = Interrupt source is disabled
bit 3-0 Unimplemented: Read as ‘0’
Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.