Datasheet

 2011-2013 Microchip Technology Inc. DS30001037C-page 79
PIC24F16KL402 FAMILY
REGISTER 8-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
— — T3GIE — — — — —
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 Unimplemented: Read as ‘0’
bit 5 T3GIF: Timer3 External Gate Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 4-0 Unimplemented: Read as ‘0’
REGISTER 8-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 U-0
— — — — —BCL2IE
(1)
SSP2IE
(1)
—
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-3 Unimplemented: Read as ‘0’
bit 2 BCL2IE: MSSP2 I
2
C™ Bus Collision Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 1 SSP2IF: MSSP2 SPI/I
2
C Event Interrupt Enable bit
(1)
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 0 Unimplemented: Read as ‘0’
Note 1: These bits are unimplemented on PIC24FXXKL10X and PIC24FXXKL20X devices.