Datasheet

2011-2013 Microchip Technology Inc. DS30001037C-page 69
PIC24F16KL402 FAMILY
REGISTER 8-1: SR: ALU STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
DC
(1)
bit 15 bit 8
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL2
(2,3)
IPL1
(2,3)
IPL0
(2,3)
RA
(1)
N
(1)
OV
(1)
Z
(1)
C
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as0
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level Status bits
(2,3)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
Note 1: See Register 3-1 for the description of these bits, which are not dedicated to interrupt control functions.
2: The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level.
The value in parentheses indicates the Interrupt Priority Level if IPL3 = 1.
3: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
Note: Bit 8 and bits 4 through 0 are described in Section 3.0 “CPU.