Datasheet

 2011-2013 Microchip Technology Inc. DS30001037C-page 49
PIC24F16KL402 FAMILY
REGISTER 5-1: NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0, HC R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
WR WREN WRERR PGMONLY
(4)
— — — —
bit 15 bit 8
U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— ERASE NVMOP5
(1)
NVMOP4
(1)
NVMOP3
(1)
NVMOP2
(1)
NVMOP1
(1)
NVMOP0
(1)
bit 7 bit 0
Legend: SO = Settable Only bit HC = Hardware Clearable bit
-n = Value at POR ‘1’ = Bit is set R = Readable bit W = Writable bit
‘0’ = Bit is cleared x = Bit is unknown U = Unimplemented bit, read as ‘0’
bit 15 WR: Write Control bit
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0 = Program or erase operation is complete and inactive
bit 14 WREN: Write Enable bit
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
bit 13 WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt, or termination, has occurred (bit is set automatically
on any set attempt of the WR bit)
0 = The program or erase operation completed normally
bit 12 PGMONLY: Program Only Enable bit
(4)
bit 11-7 Unimplemented: Read as ‘0’
bit 6 ERASE: Erase/Program Enable bit
1 = Performs the erase operation specified by NVMOP<5:0> on the next WR command
0 = Performs the program operation specified by NVMOP<5:0> on the next WR command
bit 5-0 NVMOP<5:0>: Programming Operation Command Byte bits
(1)
Erase Operations (when ERASE bit is ‘1’):
1010xx = Erases entire boot block (including code-protected boot block)
(2)
1001xx = Erases entire memory (including boot block, configuration block, general block)
(2)
011010 = Erases 4 rows of Flash memory
(3)
011001 = Erases 2 rows of Flash memory
(3)
011000 = Erases 1 row of Flash memory
(3)
0101xx = Erases entire configuration block (except code protection bits)
0100xx = Erases entire data EEPROM
(4)
0011xx = Erases entire general memory block programming operations
0001xx = Writes 1 row of Flash memory (when ERASE bit is ‘0’)
(3)
Note 1: All other combinations of the NVMOP<5:0> bits are no operation.
2: Available in ICSP™ mode only. Refer to the device programming specification.
3: The address in the Table Pointer decides which rows will be erased.
4: This bit is used only while accessing data EEPROM. It is implemented only in devices with data EEPROM.