Datasheet

PIC24F16KL402 FAMILY
DS30001037C-page 28  2011-2013 Microchip Technology Inc.
3.2 CPU Control Registers
REGISTER 3-1: SR: ALU STATUS REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — —DC
bit 15 bit 8
R/W-0
(1)
R/W-0
(1)
R/W-0
(1)
R-0 R/W-0 R/W-0 R/W-0 R/W-0
IPL2
(2)
IPL1
(2)
IPL0
(2)
RA N OV Z C
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-9 Unimplemented: Read as ‘0’
bit 8 DC: ALU Half Carry/Borrow bit
1 = A carry-out from the 4
th
low-order bit (for byte-sized data) or 8
th
low-order bit (for word-sized data)
of the result occurred
0 = No carry-out from the 4
th
or 8
th
low-order bit of the result has occurred
bit 7-5 IPL<2:0>: CPU Interrupt Priority Level (IPL) Status bits
(1,2)
111 = CPU Interrupt Priority Level is 7 (15); user interrupts disabled
110 = CPU Interrupt Priority Level is 6 (14)
101 = CPU Interrupt Priority Level is 5 (13)
100 = CPU Interrupt Priority Level is 4 (12)
011 = CPU Interrupt Priority Level is 3 (11)
010 = CPU Interrupt Priority Level is 2 (10)
001 = CPU Interrupt Priority Level is 1 (9)
000 = CPU Interrupt Priority Level is 0 (8)
bit 4 RA: REPEAT Loop Active bit
1 = REPEAT loop in progress
0 = REPEAT loop not in progress
bit 3 N: ALU Negative bit
1 = Result was negative
0 = Result was non-negative (zero or positive)
bit 2 OV: ALU Overflow bit
1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation
0 = No overflow has occurred
bit 1 Z: ALU Zero bit
1 = An operation, which effects the Z bit, has set it at some time in the past
0 = The most recent operation, which effects the Z bit, has cleared it (i.e., a non-zero result)
bit 0 C: ALU Carry/Borrow
bit
1 = A carry-out from the Most Significant bit (MSb) of the result occurred
0 = No carry-out from the Most Significant bit (MSb) of the result occurred
Note 1: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
2: The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority
Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.