Datasheet

PIC24F16KL402 FAMILY
DS30001037C-page 256  2011-2013 Microchip Technology Inc.
T
Timer1............................................................................... 115
Timer2............................................................................... 117
Timer3............................................................................... 119
Oscillator ...................................................................119
Overflow Interrupt ..................................................... 119
Timer4............................................................................... 123
PR4 Register.............................................................123
TMR4 Register.......................................................... 123
TMR4 to PR4 Match Interrupt ................................... 123
Timing Diagrams
Capture/Compare/PWM (ECCP1, ECCP2) .............. 214
CLKO and I/O ........................................................... 212
Example SPI Master Mode (CKE = 0) ...................... 215
Example SPI Master Mode (CKE = 1) ...................... 216
Example SPI Slave Mode (CKE = 0) ........................ 217
Example SPI Slave Mode (CKE = 1) ........................ 218
External Clock........................................................... 210
I
2
C Bus Data.............................................................219
I
2
C Bus Start/Stop Bits..............................................219
MSSPx I
2
C Bus Data ................................................222
MSSPx I
2
C Bus Start/Stop Bits................................. 221
Timing Requirements
A/D Conversion ......................................................... 224
Capture/Compare/PWM (ECCP1, ECCP2) .............. 214
CLKO and I/O ........................................................... 212
Comparator ............................................................... 213
Comparator Voltage Reference Settling Time .......... 213
External Clock........................................................... 210
I
2
C Bus Data (Slave Mode)....................................... 220
I
2
C Bus Data Requirements (Master Mode) ............. 222
I
2
C Bus Start/Stop Bits (Master Mode) ..................... 221
I
2
C Bus Start/Stop Bits (Slave Mode) ....................... 219
PLL Clock Specifications .......................................... 211
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset.............. 213
SPI Mode (Master Mode, CKE = 0) .......................... 215
SPI Mode (Master Mode, CKE = 1) .......................... 216
SPI Slave Mode (CKE = 1) ....................................... 218
Timing Requirements SPI Mode (Slave Mode,
CKE = 0) ................................................................... 217
U
UART ................................................................................ 149
Baud Rate Generator (BRG) .................................... 150
Break and Sync Transmit Sequence ........................ 151
IrDA Support............................................................. 151
Operation of UxCTS
and UxRTS Control Pins ......... 151
Receiving in 8-Bit or 9-Bit Data Mode....................... 151
Transmitting in 8-Bit Data Mode ............................... 151
Transmitting in 9-Bit Data Mode ............................... 151
Unique ID.......................................................................... 182
W
Watchdog Timer (WDT).................................................... 184
Windowed Operation ................................................ 184
WWW Address ................................................................. 257
WWW, On-Line Support ....................................................... 7