Datasheet

PIC24F16KL402 FAMILY
DS30001037C-page 218  2011-2013 Microchip Technology Inc.
FIGURE 26-10: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)
TABLE 26-30: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1)
Param
No.
Symbol Characteristic Min Max Units Conditions
70 T
SSL2SCH,
T
SSL2SCL
SSx
 to SCKx  or SCKx  Input 3 TCY —ns
70A TSSL2WB SSx to Write to SSPxBUF 3 TCY —ns
71 TSCH SCKx Input High Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
71A Single Byte 40 — ns (Note 1)
72 T
SCL SCKx Input Low Time
(Slave mode)
Continuous 1.25 TCY + 30 — ns
72A Single Byte 40 — ns (Note 1)
73A TB2B Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 — ns (Note 2)
74 T
SCH2DIL,
T
SCL2DIL
Hold Time of SDIx Data Input to SCKx Edge 40 — ns
75 T
DOR SDOx Data Output Rise Time — 25 ns
76 T
DOF SDOx Data Output Fall Time — 25 ns
77 T
SSH2DOZ SSx  to SDOx Output High-Impedance 10 50 ns
80 T
SCH2DOV,
T
SCL2DOV
SDOx Data Output Valid After SCKx Edge — 50 ns
82 T
SSL2DOV SDOx Data Output Valid After SSx  Edge — 50 ns
83 T
SCH2SSH,
T
SCL2SSH
SSx
 After SCKx Edge 1.5 TCY + 40 — ns
F
SCK SCKx Frequency — 10 MHz
Note 1: Requires the use of Parameter 73A.
2: Only if Parameters 71A and 72A are used.
SSx
SCKx
(CKP = 0)
SCKx
(CKP = 1)
SDOx
71 72
82
SDIx
74
75, 76
MSb bit 6 - - - - - - 1 LSb
77
bit 6 - - - - 1 LSb In
80
83
73
MSb In
Note: Refer to Figure 26-3 for load conditions.
70