Datasheet

PIC24F16KL402 FAMILY
DS30001037C-page 180  2011-2013 Microchip Technology Inc.
REGISTER 23-6: FPOR: RESET CONFIGURATION REGISTER
R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 U-0 R/P-1 R/P-1
MCLRE
(1)
BORV1
(2)
BORV0
(2)
I2C1SEL
(3)
PWRTEN — BOREN1 BOREN0
bit 7 bit 0
Legend:
R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 MCLRE: MCLR
Pin Enable bit
(1)
1 = MCLR pin is enabled; RA5 input pin is disabled
0 = RA5 input pin is enabled; MCLR
is disabled
bit 6-5 BORV<1:0>: Brown-out Reset Enable bits
(2)
11 = Brown-out Reset is set to the low trip point
10 = Brown-out Reset is set to the middle trip point
01 = Brown-out Reset is set to the high trip point
00 = Downside protection on POR is enabled (Low-Power BOR is selected)
bit 4 I2C1SEL: Alternate MSSP1 I
2
C™ Pin Mapping bit
(3)
1 = Default location for SCL1/SDA1 pins (RB8 and RB9)
0 = Alternate location for SCL1/SDA1 pins (ASCL1/RB6 and ASDA1/RB5)
bit 3 PWRTEN: Power-up Timer Enable bit
1 = PWRT is enabled
0 = PWRT is disabled
bit 2 Unimplemented: Read as ‘0’
bit 1-0 BOREN<1:0>: Brown-out Reset Enable bits
11 = BOR is enabled in hardware; SBOREN bit is disabled
10 = BOR is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled
01 = BOR is controlled with the SBOREN bit setting
00 = BOR is disabled in hardware; SBOREN bit is disabled
Note 1: The MCLRE fuse can only be changed when using the V
PP-Based ICSP™ mode entry. This prevents a
user from accidentally locking out the device from the low-voltage test entry.
2: Refer to Table 26-5 for BOR trip point voltages.
3: Implemented in 28-pin devices only. This bit position must be programmed (= 1) in all other devices for I
2
C
functionality to be available.