Datasheet

 2011-2013 Microchip Technology Inc. DS30001037C-page 175
PIC24F16KL402 FAMILY
23.0 SPECIAL FEATURES
PIC24F16KL402 family devices include several
features intended to maximize application flexibility and
reliability, and minimize cost through elimination of
external components. These are:
• Flexible Configuration
• Watchdog Timer (WDT)
• Code Protection
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
• Factory Programmed Unique ID
23.1 Code Protect Security Options
The Boot Segment (BS) and General Segment (GS)
are two segments on this device with separate
programmable security levels. The Boot Segment, con-
figured via the FBS Configuration register, can have
three possible levels of security:
• No Security (BSS = 111): The Boot Segment is
not utilized and all addresses in program memory
are part of the General Segment (GS).
• Standard Security (BSS = 110 or 101): The
Boot Segment is enabled and code-protected,
preventing ICSP reads of the Flash memory.
Standard security also prevents Flash reads and
writes of the BS from the GS. The BS can still
read and write to itself.
• High Security (BSS = 010 or 001): The Boot
Segment is enabled with all of the security pro-
vided by Standard Security mode. In addition, in
High-Security mode, there are program flow
change restrictions in place. While executing from
the GS, program flow changes that attempt to enter
the BS (e.g., branch (BRA) or CALL instructions)
can only enter the BS at one of the first 32 instruc-
tion locations (0x200 to 0x23F). Attempting to jump
into the BS at an instruction higher than this will
result in an Illegal Opcode Reset.
The General Segment, configured via the FGS Config-
uration register, can have two levels of security:
• No Security (GSS0 = 1): The GS is not
code-protected and can be read in all modes.
• Standard Security (GSS0 = 0): The GS is
code-protected, preventing ICSP reads of the
Flash memory.
For more detailed information on these Security
modes, refer to the “dsPIC33/PIC24 Family Reference
Manual”, “CodeGuard™ Security” (DS70199).
23.2 Configuration Bits
The Configuration bits can be programmed (read as ‘0’),
or left unprogrammed (read as ‘1’), to select various
device configurations. These bits are mapped starting at
program memory location, F80000h. A complete list is
provided in Table 23-1. A detailed explanation of the
various bit functions is provided in Register 23-1 through
Register 23-7.
The address, F80000h, is beyond the user program
memory space. In fact, it belongs to the configuration
memory space (800000h-FFFFFFh), which can only be
accessed using Table Reads and Table Writes.
TABLE 23-1: CONFIGURATION REGISTERS
LOCATIONS
Note: This data sheet summarizes the features of
this group of PIC24F devices. It is not
intended to be a comprehensive reference
source. For more information on the
Watchdog Timer, High-Level Device
Integration and Programming Diagnostics,
refer to the individual sections of the
“dsPIC33/PIC24 Family Reference
Manual” provided below:
• “Watchdog Timer (WDT)” (DS39697)
• “High-Level Integration with
Programmable High/Low-Voltage
Detect (HLVD)” (DS39725)
• “Programming and Diagnostics”
(DS39716)
Configuration
Register
Address
FBS F80000
FGS F80004
FOSCSEL F80006
FOSC F80008
FWDT F8000A
FPOR F8000C
FICD F8000E