Datasheet

PIC24F16KL402 FAMILY
DS30001037C-page 170  2011-2013 Microchip Technology Inc.
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Comparator Channel Select bits
11 = Inverting input of the comparator connects to V
BG/2
10 = Inverting input of the comparator connects to the CxIND pin
(2)
01 = Inverting input of the comparator connects to the CxINC pin
(2)
00 = Inverting input of the comparator connects to the CxINB pin
REGISTER 20-1: CMxCON: COMPARATOR x CONTROL REGISTER (CONTINUED)
Note 1: If EVPOL<1:0> is set to a value other than ‘00’, the first interrupt generated will occur on any transition of
COUT, regardless of if it is a rising or falling edge. Subsequent interrupts will occur based on the EVPOLx
bits setting.
2: Unimplemented on 14-pin (PIC24FXXKL100/200) devices.
REGISTER 20-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER
R/W-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC
CMIDL
— — — — — C2EVT
(1)
C1EVT
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 R-0, HSC R-0, HSC
— — — — — —C2OUT
(1)
C1OUT
bit 7 bit 0
Legend: HSC = Hardware Settable/Clearable bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CMIDL: Comparator Stop in Idle Mode bit
1 = Discontinues operation of all comparators when device enters Idle mode
0 = Continues operation of all enabled comparators in Idle mode
bit 14-10 Unimplemented: Read as ‘0’
bit 9 C2EVT: Comparator 2 Event Status bit (read-only)
(1)
Shows the current event status of Comparator 2 (CM2CON<9>).
bit 8 C1EVT: Comparator 1 Event Status bit (read-only)
Shows the current event status of Comparator 1 (CM1CON<9>).
bit 7-2 Unimplemented: Read as ‘0’
bit 1 C2OUT: Comparator 2 Output Status bit (read-only)
(1)
Shows the current output of Comparator 2 (CM2CON<8>).
bit 0 C1OUT: Comparator 1 Output Status bit (read-only)
Shows the current output of Comparator 1 (CM1CON<8>).
Note 1: These bits are unimplemented on PIC24FXXKL10X/20X devices.