Datasheet

 2011-2013 Microchip Technology Inc. DS30001037C-page 163
PIC24F16KL402 FAMILY
REGISTER 19-5: AD1CSSL: A/D INPUT SCAN SELECT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL<15:8>
(1)
bit 15 bit 8
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
CSSL<7:6>
— CSSL<4:0>
(1)
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-6 CSSL<15:6>: A/D Input Pin Scan Selection bits
(1)
1 = Corresponding analog channel selected for input scan
0 = Analog channel omitted from input scan
bit 5 Unimplemented: Read as ‘0’
bit 4-0 CSSL<4:0>: A/D Input Pin Scan Selection bits
(1)
1 = Corresponding analog channel selected for input scan
0 = Analog channel omitted from input scan
Note 1: CSSL<12:11,4:2> bits are unimplemented on 14-pin devices.
REGISTER 19-6: ANCFG: ANALOG INPUT CONFIGURATION REGISTER
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
— — — — — — — —
bit 15 bit 8
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
— — — — — — — VBGEN
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-1 Unimplemented: Read as ‘0’
bit 0 VBGEN: Internal Band Gap Reference Enable bit
1 = Internal band gap voltage is available as a channel input to the A/D Converter
0 = Band gap is not available to the A/D Converter