Datasheet

PIC24F16KL402 FAMILY
DS30001037C-page 162 2011-2013 Microchip Technology Inc.
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REGISTER 19-4: AD1CHS: A/D INPUT SELECT REGISTER
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NB CH0SB3 CH0SB2 CH0SB1 CH0SB0
bit 15 bit 8
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
CH0NA
CH0SA3 CH0SA2 CH0SA1 CH0SA0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
R-
bit 14-12 Unimplemented: Read as0
bit 11-8 CH0SB<3:0>: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits
1111 = AN15
1110 = AN14
1101 = AN13
1100 = AN12
(1)
1011 = AN11
(1)
1010 = AN10
1001 = AN9
1000 = Upper guardband rail (0.785 * V
DD)
0111 = Lower guardband rail (0.215 * V
DD)
0110 = Internal band gap reference (V
BG)
0101 = Reserved; do not use
0100 = AN4
(1)
0011 = AN3
(1)
0010 = AN2
(1)
0001 = AN1
0000 = AN0
bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is V
R-
bit 6-4 Unimplemented: Read as0
bit 3-0 CH0SA<3:0>: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits
Bit combinations are identical to those for CH0SB<3:0> (above).
Note 1: Unimplemented on 14-pin devices; do not use.