Datasheet
PIC24F16KL402 FAMILY
DS30001037C-page 160 2011-2013 Microchip Technology Inc.
REGISTER 19-2: AD1CON2: A/D CONTROL REGISTER 2
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0
VCFG2 VCFG1 VCFG0 OFFCAL
(1)
— CSCNA — —
bit 15 bit 8
R-x U-0 R/W-0 R/W-0 R/W-0 R/W-0 r-0 R/W-0
r — SMPI3 SMPI2 SMPI1 SMPI0 rALTS
bit 7 bit 0
Legend: r = Reserved bit
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
bit 12 OFFCAL: Offset Calibration bit
(1)
1 = Conversions to get the offset calibration value
0 = Conversions to get the actual input value
bit 11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Scan Input Selections for MUX A Input Multiplexer bit
1 = Scans inputs
0 = Does not scan inputs
bit 9-8 Unimplemented: Read as ‘0’
bit 7 Reserved: Ignore this value
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 =
•
• = Reserved, do not use (may cause conversion data loss)
•
0010 =
0001 = Interrupts at the completion of conversion for each 2
nd
sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 Reserved: Always maintain as ‘0’
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses MUX A input multiplexer settings for the first sample, then alternates between MUX B and
MUX A input multiplexer settings for all subsequent samples
0 = Always uses MUX A input multiplexer settings
Note 1: When the OFFCAL bit is set, inputs are disconnected and tied to AV
SS. This sets the inputs of the A/D to
zero. Then, the user can perform a conversion. Use of the Calibration mode is not affected by AD1PCFG
contents nor channel input selection. Any analog input switches are disconnected from the A/D Converter
in this mode. The conversion result is stored by the user software and used to compensate subsequent
conversions. This can be done by adding the two’s complement of the result obtained with the OFFCAL bit
set to all normal A/D conversions.
VCFG<2:0> VR+VR-
000 AV
DD AVSS
001 External VREF+ pin AVSS
010 AVDD External VREF- pin
011 External VREF+ pin External VREF- pin
1xx AVDD AVSS